25 lines
409 B
Verilog
25 lines
409 B
Verilog
`include "not16.v"
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module Not16_test;
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reg [15:0] in;
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wire [15:0] out;
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integer i;
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initial begin
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$dumpfile("not16_tb.vcd");
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$dumpvars;
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for (i=0; i<16; i=i+1)
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in[i]=0;
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for (i=15; i>=0; i=i-1)
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begin
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in[i]=1;
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#1;
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in[i]=0;
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end
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$finish();
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end
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Not16 u1 (.in(in), .out(out));
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endmodule
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