16-bit NOT

This commit is contained in:
2024-06-13 13:24:54 -07:00
parent 841881d543
commit a88adbf6e3
3 changed files with 48 additions and 0 deletions

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@@ -1,6 +1,15 @@
clean:
-rm *.vcd *.vvp
not16_tb: not16_tb.vcd
gtkwave not16_tb.vcd &
not16_tb.vcd: not16_tb.vvp
vvp not16_tb.vvp
not16_tb.vvp: not16.v not16_tb.v
iverilog -o not16_tb.vvp not16_tb.v
mux_tb: mux_tb.vcd
gtkwave mux_tb.vcd &

15
not16.v Normal file
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`ifndef _not16_v
`define _not16_v
`include "not.v"
module Not16 (input [15:0] in, output [15:0] out);
genvar i;
generate
for (i=0; i<16; i=i+1)
Not u1 (.in(in[i]), .out(out[i]));
endgenerate
endmodule
`endif

24
not16_tb.v Normal file
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`include "not16.v"
module Not16_test;
reg [15:0] in;
wire [15:0] out;
integer i;
initial begin
$dumpfile("not16_tb.vcd");
$dumpvars;
for (i=0; i<16; i=i+1)
in[i]=0;
for (i=15; i>=0; i=i-1)
begin
in[i]=1;
#1;
in[i]=0;
end
$finish();
end
Not16 u1 (.in(in), .out(out));
endmodule