16-bit NOT
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9
Makefile
9
Makefile
@@ -1,6 +1,15 @@
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clean:
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-rm *.vcd *.vvp
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not16_tb: not16_tb.vcd
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gtkwave not16_tb.vcd &
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not16_tb.vcd: not16_tb.vvp
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vvp not16_tb.vvp
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not16_tb.vvp: not16.v not16_tb.v
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iverilog -o not16_tb.vvp not16_tb.v
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mux_tb: mux_tb.vcd
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gtkwave mux_tb.vcd &
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15
not16.v
Normal file
15
not16.v
Normal file
@@ -0,0 +1,15 @@
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`ifndef _not16_v
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`define _not16_v
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`include "not.v"
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module Not16 (input [15:0] in, output [15:0] out);
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genvar i;
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generate
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for (i=0; i<16; i=i+1)
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Not u1 (.in(in[i]), .out(out[i]));
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endgenerate
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endmodule
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`endif
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24
not16_tb.v
Normal file
24
not16_tb.v
Normal file
@@ -0,0 +1,24 @@
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`include "not16.v"
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module Not16_test;
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reg [15:0] in;
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wire [15:0] out;
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integer i;
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initial begin
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$dumpfile("not16_tb.vcd");
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$dumpvars;
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for (i=0; i<16; i=i+1)
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in[i]=0;
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for (i=15; i>=0; i=i-1)
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begin
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in[i]=1;
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#1;
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in[i]=0;
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end
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$finish();
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end
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Not16 u1 (.in(in), .out(out));
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endmodule
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