22 lines
310 B
Verilog
22 lines
310 B
Verilog
`include "not.v"
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module Not_test;
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reg in=0;
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wire out;
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integer i;
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initial begin
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$dumpfile("not_tb.vcd");
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$dumpvars;
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for (i=0; i<2; i=i+1)
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begin
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in=i;
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#1;
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end
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$finish();
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end
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Not u1(.in(in), .out(out));
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endmodule
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