19 lines
495 B
Verilog
19 lines
495 B
Verilog
`ifndef _or8way_v
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`define _or8way_v
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`include "or.v"
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module Or8Way (input [7:0] in, output out);
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wire tmp00, tmp01, tmp02, tmp03, tmp10, tmp11;
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Or u1 (.a(in[0]), .b(in[1]), .out(tmp00));
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Or u2 (.a(in[2]), .b(in[3]), .out(tmp01));
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Or u3 (.a(in[4]), .b(in[5]), .out(tmp02));
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Or u4 (.a(in[6]), .b(in[7]), .out(tmp03));
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Or u5 (.a(tmp00), .b(tmp01), .out(tmp10));
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Or u6 (.a(tmp02), .b(tmp03), .out(tmp11));
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Or u7 (.a(tmp10), .b(tmp11), .out(out));
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endmodule
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`endif
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