8-input OR

Makefile

@@ -1,6 +1,15 @@
 clean:
 	-rm *.vcd *.vvp
 
+or8way_tb: or8way_tb.vcd
+	gtkwave or8way_tb.vcd &
+
+or8way_tb.vcd: or8way_tb.vvp
+	vvp or8way_tb.vvp
+
+or8way_tb.vvp: or8way.v or8way_tb.v
+	iverilog -o or8way_tb.vvp or8way_tb.v
+
 mux16_tb: mux16_tb.vcd
 	gtkwave mux16_tb.vcd &
 

or8way.v

@@ -0,0 +1,18 @@
+`ifndef _or8way_v
+`define _or8way_v
+
+`include "or.v"
+
+module Or8Way (input [7:0] in, output out);
+    wire tmp00, tmp01, tmp02, tmp03, tmp10, tmp11;
+
+    Or u1 (.a(in[0]), .b(in[1]), .out(tmp00));
+    Or u2 (.a(in[2]), .b(in[3]), .out(tmp01));
+    Or u3 (.a(in[4]), .b(in[5]), .out(tmp02));
+    Or u4 (.a(in[6]), .b(in[7]), .out(tmp03));
+    Or u5 (.a(tmp00), .b(tmp01), .out(tmp10));
+    Or u6 (.a(tmp02), .b(tmp03), .out(tmp11));
+    Or u7 (.a(tmp10), .b(tmp11), .out(out));
+endmodule
+
+`endif

or8way_tb.v

@@ -0,0 +1,21 @@
+`include "or8way.v"
+
+module Or8Way_test;
+    reg [7:0] in;
+    wire out;
+
+    integer i;
+
+    initial begin
+        $dumpfile("or8way_tb.vcd");
+        $dumpvars;
+        for (i=0; i<256; i=i+1)
+        begin
+            in=i;
+            #1;
+        end
+        $finish();
+    end
+
+    Or8Way u1(.in(in), .out(out));
+endmodule