sci-electronics/yosys: version bump

2024-12-11 16:55:01 +00:00
parent 5324095d79
commit 5b22142176
2 changed files with 2 additions and 2 deletions
--- a/metadata/md5-cache/sci-electronics/yosys-0.48
+++ b/metadata/md5-cache/sci-electronics/yosys-0.48
@@ -10,4 +10,4 @@ LICENSE=ISC
 PROPERTIES=live
 SLOT=0
 _eclasses_=git-r3	875eb471682d3e1f18da124be97dcc81
-_md5_=180368382f349638912c4258ad87dc0f
+_md5_=c31438e098c25b49fe21cb1e0ab58f72
--- a/sci-electronics/yosys/yosys-0.48.ebuild
+++ b/sci-electronics/yosys/yosys-0.48.ebuild
@@ -5,7 +5,7 @@ inherit git-r3
 DESCRIPTION="framework for Verilog RTL synthesis"
 HOMEPAGE="http://www.clifford.at/yosys/"
 EGIT_REPO_URI=https://github.com/YosysHQ/yosys
-EGIT_COMMIT=$PV
+EGIT_COMMIT=v$PV
 LICENSE=ISC
 SLOT=0
 KEYWORDS=amd64