This converts PCB/Schematic files to KiCad 7 format. Converted by simply
opening the project and press save.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Added:
- solderable standoffs for the CM4
- DC_IN_F pulldown for D2 high temp reverse current control R44
Modified:
- USB recovery jumper JP2 replaced with a button SW3
- R64 changed to 33k from 6.8k
Previous versions used R44/R60 with 0.1Ohm in parallel for easier
testing. However, with the final version, only the frootprint for
R60 is in the layout, hence it has to be 0.05Ohm.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Adjust silk screen graphics to match current layout. Adjust silk screen
reference designator placements. Bump date and version of schematics and
PCB.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Various BOM adjustments, most notably setting/correcting manufacturer
and part number information for D22, D30, FL1, L4 and L5.
Signed-off-by: Stefan Agner <stefan@agner.ch>
-eth shield is not connected to the GND rather it shields "input" of poe
-used smaller package for bulk PoE capacitor
-Changed common mode filter to Pulse T8113
-Added more inductor filters on the primary side
-replaced secondary side ferrite silter with an inductor
-used distributed "flyback" capacitor (3 instead of 1)
-slightly increased distance between the poe transformer and the
ethernet signal traces
- extended GND1 under the transformer
- primary snubber circuit is now in "hot-loop" area
-repositioned poe enable optocoupler
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
-Snubber circuit under ecrtail load condition can dissipate more power
then the resistor can handle, increased the resistor size and added one
more in parallel
-Increased size of some of the 12V input capacitors
-Use 3.3Vp instead of 3.3V generated by the RPi for LED, RTC, Radio, Fan
control and RPi reduced hat connector
-PoE pri/sec capacitor value changed
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
decreased coupling between poe lines and the gnd plane
added vias to stich main gnd planes
decreased the peak current through the transformer
inductor based pi filter on the poe output
decreased coupling to gnd of the poe "noise path"
added parallel mosfet capacitance to poe
moved fb line fo the dcdcs away from inductors
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Increment to sub-version v1.2. Main changes are:
- Back and front silk screen
- LED resistors
There are no changes in the layout and any critical components.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Cleanup some fill zones.
Updated the Transformer symbol with pin 4, connected to +48V for better
zone fill.
fixed top/bottom transition for the DC_IN_F
Added some gnd vias
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Modified PoE layout to account for GNDS-GND1 flow
and repositioned the noise retern capacitor.
Snubber was corrected for the transformer used and the switching
frequency. Some components were removed.
PoE Input filter was adjusted.
3.3 and 5V DCDC capacitor layout was optimised and unused components
were removed.
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
- Fix edge cut on lower right corner to make board size exact
- Update board charactristics
- Set grid origin back to 30, 30
- Update M.2 expansion silk screen (remove AI accelerator hint)
- Various silk screen reference designator fixes/improvements
- Add ESD warning logo
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Update silk screen reference designators
- Update backside silk screen for Yellow revision 1.1
- Set U21 (SOIC-8 RTC) to assemble and U25 (MSOP-8) as DNP
- Update heatsink footprint to add heatsink outline to silk screen (#44)
- Mark orientation of D26, D27, D28 and D29 (fixes#39)
- Use pin-header footprint for PoE selector J13, it is now JP5
Signed-off-by: Stefan Agner <stefan@agner.ch>
-Fixed upstream diff pair polarity
-added optional inverer for the USB power switch enable pin
Design now supports both AP2181 and AP2191
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Run annotation again which just updated some net names. Address various
DRC issues like courtyard violence and exclude the remaining DRC errors.
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Change FL1 to be Murata Electronics DLW5BTM102SQ2. This version is not
automotive approved. It is cheaper and has better availability
currently.
Signed-off-by: Stefan Agner <stefan@agner.ch>
- U7: Define Manufacturer/PartNumber
- J13: Define Manufacturer/PartNumber
- L2: Fix PartNumber (remove unprintable characters)
- C85: Change to our preferred supplier Nichicon
- J9: DNP (not used by default, avoid potential issues with FCC approval)
- Y1/Y2: Define frequency and load capacitance in value
- JP1: Use sensible part value
- C106: Fix Config field
- Remove heat sink and CM4 from BOM (handled in product assembly BOM)
Signed-off-by: Stefan Agner <stefan@agner.ch>
PoE
-Added a common mode filter on the input
-FB filter on the output side
-12V in now disables the poe with the DEN pin
-DT is now disabled
-PSRS is now disabled
-move to 1210 resistors for resistors identified in thermal testing
-DTHR is now enabled in default BoM
-some resistor values were adjusted
-some caps were moved to the common power supply section
USB:
-USB Hub 1.8V rail have capacitors added
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
updates
schematic:
-change usb current protection IC to 1.5A
-Added low-pass filter to the audio output
-PoE fixed primary windings polarity
-added option to select poe class with a jumper (between 3 and 4)
-fixes in poe design
-added testpoints
-added virtual hirose df40c connectors for pick and place use
lightblue.pretty:
-added fake DF40C footprint for pick and place and 3d model purposes
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2.2uF/100V are not really available in a 0805 package. This part of
the PoE design a 25V rating is sufficent.
Fixes: #22
Signed-off-by: Stefan Agner <stefan@agner.ch>
Order some relevant reference designator. Use JP for all jumpers. Place
silkcreen neatly. Add some custom silk screen. Remove heat sink corner
marks on silk screen.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Changes:
Footrints:
-Modified DC Jack to accomodate CUI PJ-002A
-Modified RJ45 to increase clearance between shield and poe pins
-Modified m.2 mounting pads to avoid drc errors
Schematic:
-usb-c facing usb mux is supplied by +3v3VP
-added misc. capacitors
PCB
-min. annular ring for vias set to 0.125 from 0.2
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
