Redesign the back silk screen. The new print provides space for a
larger label (32x19mm), uses the new Powered By Raspberry Pi logo and
prints "Made in PRC" onto the PCB.
Fixes: #52, #55
Signed-off-by: Stefan Agner <stefan@agner.ch>
Use the recommended hole size of 4.22mm. Make the outer diameter
slightly larger than specified as minimum to allow more space for excess
solder.
Fixes: #54
Signed-off-by: Stefan Agner <stefan@agner.ch>
Previous versions used R44/R60 with 0.1Ohm in parallel for easier
testing. However, with the final version, only the frootprint for
R60 is in the layout, hence it has to be 0.05Ohm.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Adjust silk screen graphics to match current layout. Adjust silk screen
reference designator placements. Bump date and version of schematics and
PCB.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Various BOM adjustments, most notably setting/correcting manufacturer
and part number information for D22, D30, FL1, L4 and L5.
Signed-off-by: Stefan Agner <stefan@agner.ch>
-eth shield is not connected to the GND rather it shields "input" of poe
-used smaller package for bulk PoE capacitor
-Changed common mode filter to Pulse T8113
-Added more inductor filters on the primary side
-replaced secondary side ferrite silter with an inductor
-used distributed "flyback" capacitor (3 instead of 1)
-slightly increased distance between the poe transformer and the
ethernet signal traces
- extended GND1 under the transformer
- primary snubber circuit is now in "hot-loop" area
-repositioned poe enable optocoupler
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
-Snubber circuit under ecrtail load condition can dissipate more power
then the resistor can handle, increased the resistor size and added one
more in parallel
-Increased size of some of the 12V input capacitors
-Use 3.3Vp instead of 3.3V generated by the RPi for LED, RTC, Radio, Fan
control and RPi reduced hat connector
-PoE pri/sec capacitor value changed
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
decreased coupling between poe lines and the gnd plane
added vias to stich main gnd planes
decreased the peak current through the transformer
inductor based pi filter on the poe output
decreased coupling to gnd of the poe "noise path"
added parallel mosfet capacitance to poe
moved fb line fo the dcdcs away from inductors
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Increment to sub-version v1.2. Main changes are:
- Back and front silk screen
- LED resistors
There are no changes in the layout and any critical components.
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Place reference properly
- Move and update Wireless smart-home text
- Move and update PoE+ text
- Readd symbols and back silkscreen (with proper attributes)
Signed-off-by: Stefan Agner <stefan@agner.ch>
In order to accomodate the C93 next to the transformer.
Added top layer GND1 pour under the transformer
shortened the GNDS path.
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Cleanup some fill zones.
Updated the Transformer symbol with pin 4, connected to +48V for better
zone fill.
fixed top/bottom transition for the DC_IN_F
Added some gnd vias
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Modified PoE layout to account for GNDS-GND1 flow
and repositioned the noise retern capacitor.
Snubber was corrected for the transformer used and the switching
frequency. Some components were removed.
PoE Input filter was adjusted.
3.3 and 5V DCDC capacitor layout was optimised and unused components
were removed.
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
- Fix edge cut on lower right corner to make board size exact
- Update board charactristics
- Set grid origin back to 30, 30
- Update M.2 expansion silk screen (remove AI accelerator hint)
- Various silk screen reference designator fixes/improvements
- Add ESD warning logo
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Update silk screen reference designators
- Update backside silk screen for Yellow revision 1.1
- Set U21 (SOIC-8 RTC) to assemble and U25 (MSOP-8) as DNP
- Update heatsink footprint to add heatsink outline to silk screen (#44)
- Mark orientation of D26, D27, D28 and D29 (fixes#39)
- Use pin-header footprint for PoE selector J13, it is now JP5
Signed-off-by: Stefan Agner <stefan@agner.ch>
