This converts PCB/Schematic files to KiCad 7 format. Converted by simply
opening the project and press save.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Added:
- solderable standoffs for the CM4
- DC_IN_F pulldown for D2 high temp reverse current control R44
Modified:
- USB recovery jumper JP2 replaced with a button SW3
- R64 changed to 33k from 6.8k
Adjust silk screen graphics to match current layout. Adjust silk screen
reference designator placements. Bump date and version of schematics and
PCB.
Signed-off-by: Stefan Agner <stefan@agner.ch>
-eth shield is not connected to the GND rather it shields "input" of poe
-used smaller package for bulk PoE capacitor
-Changed common mode filter to Pulse T8113
-Added more inductor filters on the primary side
-replaced secondary side ferrite silter with an inductor
-used distributed "flyback" capacitor (3 instead of 1)
-slightly increased distance between the poe transformer and the
ethernet signal traces
- extended GND1 under the transformer
- primary snubber circuit is now in "hot-loop" area
-repositioned poe enable optocoupler
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
-Snubber circuit under ecrtail load condition can dissipate more power
then the resistor can handle, increased the resistor size and added one
more in parallel
-Increased size of some of the 12V input capacitors
-Use 3.3Vp instead of 3.3V generated by the RPi for LED, RTC, Radio, Fan
control and RPi reduced hat connector
-PoE pri/sec capacitor value changed
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
decreased coupling between poe lines and the gnd plane
added vias to stich main gnd planes
decreased the peak current through the transformer
inductor based pi filter on the poe output
decreased coupling to gnd of the poe "noise path"
added parallel mosfet capacitance to poe
moved fb line fo the dcdcs away from inductors
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Modified PoE layout to account for GNDS-GND1 flow
and repositioned the noise retern capacitor.
Snubber was corrected for the transformer used and the switching
frequency. Some components were removed.
PoE Input filter was adjusted.
3.3 and 5V DCDC capacitor layout was optimised and unused components
were removed.
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
- Update silk screen reference designators
- Update backside silk screen for Yellow revision 1.1
- Set U21 (SOIC-8 RTC) to assemble and U25 (MSOP-8) as DNP
- Update heatsink footprint to add heatsink outline to silk screen (#44)
- Mark orientation of D26, D27, D28 and D29 (fixes#39)
- Use pin-header footprint for PoE selector J13, it is now JP5
Signed-off-by: Stefan Agner <stefan@agner.ch>
