Dominik Sliwa d70d55928a [WIP] PCB design
Done:
PoE - primary side,
DCDC location,
USB hub location,

TBD:
HUB routing,
PoE sec. side,
Audio

Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2021-08-24 01:13:22 +02:00
2021-08-12 20:20:45 +02:00
2021-01-17 11:02:12 +01:00
2021-01-12 20:03:39 +01:00
2021-08-12 20:20:45 +02:00
2021-08-24 01:13:22 +02:00
2021-08-18 12:16:09 +02:00
2021-08-15 01:02:49 +02:00
2021-08-12 20:20:45 +02:00
2021-08-12 20:20:45 +02:00
2021-08-18 12:16:09 +02:00
2021-08-18 12:16:09 +02:00
2021-08-12 20:20:45 +02:00
Description
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32 MiB
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KiCad Schematic 100%