Update OSX build instructions.

Fix a few minor build tweaks.

.appveyor.yml

@@ -15,7 +15,7 @@ install:
 
 build_script:
   - make
-  - zip -9 fluxengine.zip fluxengine.exe brother120tool.exe cwftoflux.exe
+  - zip -9 fluxengine.zip fluxengine.exe brother120tool.exe FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex
 
 artifacts:
   - path: fluxengine.zip

.github/workflows/ccpp.yml

@@ -0,0 +1,34 @@
+name: C/C++ CI
+
+on: [push]
+
+jobs:
+  build-linux:
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v1
+    - name: apt
+      run: sudo apt install libusb-1.0-0-dev libsqlite3-dev ninja-build
+    - name: make
+      run: make
+
+  build-macos:
+    runs-on: macos-latest
+    steps:
+    - uses: actions/checkout@v1
+    - name: brew
+      run: brew install sqlite pkg-config libusb ninja
+    - name: make
+      run: make
+
+#  build-windows:
+#    runs-on: windows-latest
+#    steps:
+#    - uses: numworks/setup-msys2@v1
+#      with:
+#        msystem: MSYS
+#    - uses: actions/checkout@v1
+#    - name: pacman
+#      run: msys2do pacman -S --noconfirm --needed make ninja mingw-w64-i686-libusb mingw-w64-i686-sqlite3 mingw-w64-i686-zlib mingw-w64-i686-gcc zip
+#    - name: make
+#      run: msys2do make

.hgignore

@@ -3,6 +3,10 @@ streams
 .*\.flux
 .*\.img
 .*\.raw
+.*\.orig
 .vscode
 remote
+FluxEngine.cydsn/CortexM3
+FluxEngine.cydsn/Generated_Source
+FluxEngine.cydsn/codegentemp
 

.travis.yml

@@ -1,39 +0,0 @@
-language: shell
-git:
-    depth: 1
-
-matrix:
-    include:
-        -
-            os: linux
-            sudo: false
-            dist: xenial
-            compiler: gcc
-            env: CXX=g++-8
-            script:
-            - make
-        -
-            os: osx
-            osx_image: xcode10.2
-            compiler: clang
-            env:
-            - HOMEBREW_NO_INSTALL_CLEANUP=1
-
-addons:
-    apt:
-        sources:
-        - llvm-toolchain-precise-3.8
-        - ubuntu-toolchain-r-test
-        packages:
-        - ninja-build
-        - libusb-1.0-0-dev
-        - libsqlite3-dev
-        - g++-8
-    homebrew:
-        packages:
-        - ninja
-
-script:
-- make
-
-

FluxEngine.cydsn/FIFOin/API/c.c

@@ -0,0 +1,27 @@
+#include "cyfitter_cfg.h"
+#include "cydevice_trm.h"
+#include "cyfitter.h"
+#include "`$INSTANCE_NAME`_h.h"
+
+void `$INSTANCE_NAME`_Start()
+{
+   `$INSTANCE_NAME`_Init();
+}    
+
+void `$INSTANCE_NAME`_Stop()
+{
+    `$INSTANCE_NAME`_Disable();
+}
+
+void `$INSTANCE_NAME`_Init()
+{    
+    `$INSTANCE_NAME`_Enable();
+    
+}
+void `$INSTANCE_NAME`_Enable()
+{
+}
+
+void `$INSTANCE_NAME`_Disable()
+{
+}

FluxEngine.cydsn/FIFOin/API/h.h

@@ -0,0 +1,50 @@
+#if !defined(`$INSTANCE_NAME`_H)
+#define `$INSTANCE_NAME`_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "CyLib.h" 
+
+#define `$INSTANCE_NAME`_FIFO_PTR	         ((reg8 *) `$INSTANCE_NAME`_dp__F0_REG)
+
+    /* Macros to clear DP FIFOs.*/
+#define `$INSTANCE_NAME`_CLEAR do { \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
+    } while(0)
+
+/* Macros to set FIFO level mode. See the TRM for details */
+#define `$INSTANCE_NAME`_SET_LEVEL_NORMAL \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfbu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+#define `$INSTANCE_NAME`_SET_LEVEL_MID \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x04u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+
+/* Macros to set FIFO to single-buffer mode. */
+#define `$INSTANCE_NAME`_SINGLE_BUFFER_SET \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+
+/* Macros to return the FIFO to normal mode. */
+#define `$INSTANCE_NAME`_SINGLE_BUFFER_UNSET \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+    
+void `$INSTANCE_NAME`_Enable();
+void `$INSTANCE_NAME`_Disable();
+void `$INSTANCE_NAME`_Start();
+void `$INSTANCE_NAME`_Stop();
+void `$INSTANCE_NAME`_Init();
+
+#endif
+
+/* [] END OF FILE */

FluxEngine.cydsn/FIFOin/FIFOin.v

@@ -0,0 +1,128 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+
+/* Ultra-simple FIFO in component: a byte is shifted in every clock when req
+ * is high. */
+ 
+module FIFOin (drq, clk, d, req);
+	output  drq;
+	input   clk;
+	input  [7:0] d;
+	input  req;
+
+//`#start body` -- edit after this line, do not edit this line
+
+wire [7:0] pi;
+assign pi = d;
+
+wire load;
+assign load = req;
+
+cy_psoc3_dp #(.cy_dpconfig(
+{
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM0:    */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM1:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM2:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM3:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM4:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM5:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM6:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM7:     */
+	8'hFF, 8'h00,	/*CFG9:     */
+	8'hFF, 8'hFF,	/*CFG11-10:     */
+	`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
+	`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
+	`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
+	`SC_SI_A_DEFSI, /*CFG13-12:     */
+	`SC_A0_SRC_PIN, `SC_SHIFT_SL, 1'h0,
+	1'h0, `SC_FIFO1_BUS, `SC_FIFO0_ALU,
+	`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
+	`SC_FB_NOCHN, `SC_CMP1_NOCHN,
+	`SC_CMP0_NOCHN, /*CFG15-14:     */
+	10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
+	`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
+	`SC_WRK16CAT_DSBL /*CFG17-16:     */
+}
+)) dp(
+	/* input          */ .clk(clk),
+	/* input [02:00]  */ .cs_addr(3'b0),    // Program counter
+	/* input          */ .route_si(1'b0),   // Shift in
+	/* input          */ .route_ci(1'b0),   // Carry in
+	/* input          */ .f0_load(load),    // Load FIFO 0
+	/* input          */ .f1_load(1'b0), 	// Load FIFO 1
+	/* input          */ .d0_load(1'b0), 	// Load Data Register 0
+	/* input          */ .d1_load(1'b0), 	// Load Data Register 1
+	/* output         */ .ce0(), 			// Accumulator 0 = Data register 0
+	/* output         */ .cl0(), 			// Accumulator 0 < Data register 0
+	/* output         */ .z0(), 			// Accumulator 0 = 0
+	/* output         */ .ff0(), 			// Accumulator 0 = FF
+	/* output         */ .ce1(), 			// Accumulator [0|1] = Data register 1
+	/* output         */ .cl1(), 			// Accumulator [0|1] < Data register 1
+	/* output         */ .z1(), 			// Accumulator 1 = 0
+	/* output         */ .ff1(), 			// Accumulator 1 = FF
+	/* output         */ .ov_msb(), 		// Operation over flow
+	/* output         */ .co_msb(), 		// Carry out
+	/* output         */ .cmsb(), 			// Carry out
+	/* output         */ .so(), 			// Shift out
+    /* output         */ .f0_bus_stat(drq), // not empty
+	/* output         */ .f0_blk_stat(full),// full
+	/* output         */ .f1_bus_stat(), 	// FIFO 1 status to uP
+	/* output         */ .f1_blk_stat(), 	// FIFO 1 status to DP
+	/* input          */ .ci(1'b0), 		// Carry in from previous stage
+	/* output         */ .co(), 			// Carry out to next stage
+	/* input          */ .sir(1'b0), 		// Shift in from right side
+	/* output         */ .sor(), 			// Shift out to right side
+	/* input          */ .sil(1'b0), 		// Shift in from left side
+	/* output         */ .sol(), 			// Shift out to left side
+	/* input          */ .msbi(1'b0), 		// MSB chain in
+	/* output         */ .msbo(), 			// MSB chain out
+	/* input [01:00]  */ .cei(2'b0),        // Compare equal in from prev stage
+	/* output [01:00] */ .ceo(),            // Compare equal out to next stage
+	/* input [01:00]  */ .cli(2'b0), 	    // Compare less than in from prv stage
+	/* output [01:00] */ .clo(),            // Compare less than out to next stage
+	/* input [01:00]  */ .zi(2'b0),         // Zero detect in from previous stage
+	/* output [01:00] */ .zo(),             // Zero detect out to next stage
+	/* input [01:00]  */ .fi(2'b0), 		// 0xFF detect in from previous stage
+	/* output [01:00] */ .fo(), 	        // 0xFF detect out to next stage
+	/* input [01:00]  */ .capi(2'b0),	    // Capture in from previous stage
+	/* output [01:00] */ .capo(),		    // Capture out to next stage
+	/* input          */ .cfbi(1'b0), 		// CRC Feedback in from previous stage
+	/* output         */ .cfbo(), 			// CRC Feedback out to next stage
+	/* input [07:00]  */ .pi(pi), 		    // Parallel data port
+	/* output [07:00] */ .po()              // Parallel data port
+);
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
+
+
+
+

FluxEngine.cydsn/FIFOout/API/c.c

@@ -0,0 +1,27 @@
+#include "cyfitter_cfg.h"
+#include "cydevice_trm.h"
+#include "cyfitter.h"
+#include "`$INSTANCE_NAME`_h.h"
+
+void `$INSTANCE_NAME`_Start()
+{
+   `$INSTANCE_NAME`_Init();
+}    
+
+void `$INSTANCE_NAME`_Stop()
+{
+    `$INSTANCE_NAME`_Disable();
+}
+
+void `$INSTANCE_NAME`_Init()
+{    
+    `$INSTANCE_NAME`_Enable();
+    
+}
+void `$INSTANCE_NAME`_Enable()
+{
+}
+
+void `$INSTANCE_NAME`_Disable()
+{
+}

FluxEngine.cydsn/FIFOout/API/h.h

@@ -0,0 +1,50 @@
+#if !defined(`$INSTANCE_NAME`_H)
+#define `$INSTANCE_NAME`_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "CyLib.h" 
+
+#define `$INSTANCE_NAME`_FIFO_PTR	         ((reg8 *) `$INSTANCE_NAME`_dp__F0_REG)
+
+    /* Macros to clear DP FIFOs.*/
+#define `$INSTANCE_NAME`_CLEAR do { \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
+    } while(0)
+
+/* Macros to set FIFO level mode. See the TRM for details */
+#define `$INSTANCE_NAME`_SET_LEVEL_NORMAL \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfbu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+#define `$INSTANCE_NAME`_SET_LEVEL_MID \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x04u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+
+/* Macros to set FIFO to single-buffer mode. */
+#define `$INSTANCE_NAME`_SINGLE_BUFFER_SET \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+
+/* Macros to return the FIFO to normal mode. */
+#define `$INSTANCE_NAME`_SINGLE_BUFFER_UNSET \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+    
+void `$INSTANCE_NAME`_Enable();
+void `$INSTANCE_NAME`_Disable();
+void `$INSTANCE_NAME`_Start();
+void `$INSTANCE_NAME`_Stop();
+void `$INSTANCE_NAME`_Init();
+
+#endif
+
+/* [] END OF FILE */

FluxEngine.cydsn/FIFOout/FIFOout.v

@@ -0,0 +1,168 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+// Generated on 11/16/2017 at 15:44
+// Component: FIFOout
+module FIFOout (
+    input req,
+	input clk,
+    output [7:0] d,
+	output drq,
+	output empty,
+    output ack
+);
+
+//`#start body` -- edit after this line, do not edit this line
+
+/* Reads from the FIFO are done based on the FIFO being not empty. */
+ 
+wire [7:0] po;
+assign d = po;
+
+localparam STATE_WAIT = 1'b0;
+localparam STATE_READ = 1'b1;
+
+reg state;
+reg oldreq;
+
+assign ack = (state != STATE_READ);
+
+always @(posedge clk)
+begin
+    case (state)
+        STATE_WAIT:
+        begin
+            if (!empty)
+            begin
+                if (req && !oldreq)
+                begin
+                    state <= STATE_READ;
+                end
+                oldreq <= req;
+            end
+        end
+        
+        STATE_READ:
+        begin
+            state <= STATE_WAIT;
+        end
+    endcase
+end
+            
+cy_psoc3_dp #(.cy_dpconfig(
+{
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM0: STATE_WAITFORREQ*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM1: STATE_LOAD*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM2:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM3:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM4:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM5:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM6:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM7:           */
+    8'hFF, 8'h00,  /*CFG9:           */
+    8'hFF, 8'hFF,  /*CFG11-10:           */
+    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
+    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
+    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
+    `SC_SI_A_DEFSI, /*CFG13-12:           */
+    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
+    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
+    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
+    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
+    `SC_CMP0_NOCHN, /*CFG15-14:           */
+    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
+    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
+    `SC_WRK16CAT_DSBL /*CFG17-16:           */
+}
+)) dp(
+        /*  input                   */  .reset(1'b0),
+        /*  input                   */  .clk(clk),
+        /*  input   [02:00]         */  .cs_addr({2'b0, state}),
+        /*  input                   */  .route_si(1'b0),
+        /*  input                   */  .route_ci(1'b0),
+        /*  input                   */  .f0_load(1'b0),
+        /*  input                   */  .f1_load(1'b0),
+        /*  input                   */  .d0_load(1'b0),
+        /*  input                   */  .d1_load(1'b0),
+        /*  output                  */  .ce0(),
+        /*  output                  */  .cl0(),
+        /*  output                  */  .z0(),
+        /*  output                  */  .ff0(),
+        /*  output                  */  .ce1(),
+        /*  output                  */  .cl1(),
+        /*  output                  */  .z1(),
+        /*  output                  */  .ff1(),
+        /*  output                  */  .ov_msb(),
+        /*  output                  */  .co_msb(),
+        /*  output                  */  .cmsb(),
+        /*  output                  */  .so(),
+        /*  output                  */  .f0_bus_stat(drq), // not full
+        /*  output                  */  .f0_blk_stat(empty), // empty
+        /*  output                  */  .f1_bus_stat(),
+        /*  output                  */  .f1_blk_stat(),
+        
+        /* input                    */  .ci(1'b0),     // Carry in from previous stage
+        /* output                   */  .co(),// Carry out to next stage
+        /* input                    */  .sir(1'b0),    // Shift in from right side
+        /* output                   */  .sor(),        // Shift out to right side
+        /* input                    */  .sil(1'b0),    // Shift in from left side
+        /* output                   */  .sol(),        // Shift out to left side
+        /* input                    */  .msbi(1'b0),   // MSB chain in
+        /* output                   */  .msbo(),       // MSB chain out
+        /* input [01:00]            */  .cei(2'b0),    // Compare equal in from prev stage
+        /* output [01:00]           */  .ceo(),        // Compare equal out to next stage
+        /* input [01:00]            */  .cli(2'b0),    // Compare less than in from prv stage
+        /* output [01:00]           */  .clo(),        // Compare less than out to next stage
+        /* input [01:00]            */  .zi(2'b0),     // Zero detect in from previous stage
+        /* output [01:00]           */  .zo(),         // Zero detect out to next stage
+        /* input [01:00]            */  .fi(2'b0),     // 0xFF detect in from previous stage
+        /* output [01:00]           */  .fo(),         // 0xFF detect out to next stage
+        /* input [01:00]            */  .capi(2'b0),   // Software capture from previous stage
+        /* output [01:00]           */  .capo(),       // Software capture to next stage
+        /* input                    */  .cfbi(1'b0),   // CRC Feedback in from previous stage
+        /* output                   */  .cfbo(),       // CRC Feedback out to next stage
+        /* input [07:00]            */  .pi(8'b0),     // Parallel data port
+        /* output [07:00]           */  .po(po)       // Parallel data port
+);
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
+
+
+
+
+
+
+
+
+
+
+
+

FluxEngine.cydsn/FluxEngine.cydwr

@@ -28,13 +28,85 @@
         <Data key="sync_with_bus_clk" value="True" />
         <Data key="user_set_domain" value="False" />
       </Group>
+      <Group key="1a7e8637-3b6b-4e84-839c-0dfc18fdaf5b">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_5" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_5" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
+      <Group key="3f3708ae-fb62-4012-919b-9a3b9a1dfbc2">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_8" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_8" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
+      <Group key="4eef02b9-8ad1-43c4-85f1-b3335faa5fc4">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_3" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_3" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
       <Group key="06c4d5d4-f15f-4b29-a1d0-c24b2e38b1ec">
         <Data key="check_tolerance" value="True" />
         <Data key="clock_version" value="v1" />
         <Data key="derive_type" value="NAMED_FREQ" />
-        <Data key="desired_freq" value="24" />
+        <Data key="desired_freq" value="12" />
         <Data key="desired_unit" value="6" />
-        <Data key="divider" value="1" />
+        <Data key="divider" value="2" />
         <Data key="domain" value="DIGITAL" />
         <Data key="enabled" value="True" />
         <Data key="minus_accuracy" value="0.25" />
@@ -50,7 +122,7 @@
         <Data key="src_clk_name" value="IMO" />
         <Data key="start_on_reset" value="True" />
         <Data key="sync_with_bus_clk" value="True" />
-        <Data key="user_set_domain" value="False" />
+        <Data key="user_set_domain" value="True" />
       </Group>
       <Group key="24cd38f7-f472-4403-837f-86807c8f5333">
         <Data key="check_tolerance" value="True" />
@@ -123,6 +195,54 @@
         <Data key="sync_with_bus_clk" value="True" />
         <Data key="user_set_domain" value="False" />
       </Group>
+      <Group key="71bc291d-84a7-40a8-b7b2-1c8a34326a31">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_FREQ" />
+        <Data key="desired_freq" value="300" />
+        <Data key="desired_unit" value="0" />
+        <Data key="divider" value="65536" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="CLOCK300" />
+        <Data key="named_src_direct_connect" value="False" />
+        <Data key="netlist_name" value="CLOCK300" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="CEF43CFB-0213-49b9-B980-2FFAB81C5B47" />
+        <Data key="src_clk_name" value="IMO" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
+      <Group key="90ce0c72-9f10-44ef-a049-f0f525d59bea">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_FREQ" />
+        <Data key="desired_freq" value="128" />
+        <Data key="desired_unit" value="0" />
+        <Data key="divider" value="65536" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="CLOCK8" />
+        <Data key="named_src_direct_connect" value="False" />
+        <Data key="netlist_name" value="CLOCK8" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="CEF43CFB-0213-49b9-B980-2FFAB81C5B47" />
+        <Data key="src_clk_name" value="IMO" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
       <Group key="349ffa20-8576-4ac3-9a6f-34ef606de6cf">
         <Data key="check_tolerance" value="True" />
         <Data key="clock_version" value="v1" />
@@ -146,6 +266,29 @@
         <Data key="sync_with_bus_clk" value="True" />
         <Data key="user_set_domain" value="False" />
       </Group>
+      <Group key="4033c29d-f4bc-4e94-ac95-aa587e869f88/696a0979-21fc-4185-bf38-6c79febcde7a">
+        <Data key="check_tolerance" value="False" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="AUTO" />
+        <Data key="desired_freq" value="1600000" />
+        <Data key="desired_unit" value="0" />
+        <Data key="divider" value="40" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="OUTPUT_VOLTAGE_ADC_theACLK" />
+        <Data key="netlist_name" value="\OUTPUT_VOLTAGE_ADC:theACLK\" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="61737EF6-3B74-48f9-8B91-F7473A442AE7" />
+        <Data key="src_clk_name" value="MASTER_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
       <Group key="6616e828-6611-4893-a674-66c861d79d6c">
         <Data key="check_tolerance" value="True" />
         <Data key="clock_version" value="v1" />
@@ -193,6 +336,101 @@
         <Data key="sync_with_bus_clk" value="True" />
         <Data key="user_set_domain" value="False" />
       </Group>
+      <Group key="75187c05-9501-4450-b306-6ccdd3bb77db">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_5" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_5" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
+      <Group key="09974428-e912-491f-8d2f-361ba50e7599">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_6" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_6" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
+      <Group key="a5825a94-fa18-4e4f-a843-bc687cacbd56/696a0979-21fc-4185-bf38-6c79febcde7a">
+        <Data key="check_tolerance" value="False" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="AUTO" />
+        <Data key="desired_freq" value="1600000" />
+        <Data key="desired_unit" value="0" />
+        <Data key="divider" value="40" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="INPUT_VOLTAGE_ADC_theACLK" />
+        <Data key="netlist_name" value="\INPUT_VOLTAGE_ADC:theACLK\" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="61737EF6-3B74-48f9-8B91-F7473A442AE7" />
+        <Data key="src_clk_name" value="MASTER_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
+      <Group key="b762c287-7f87-4b21-982e-84be01dc5115">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_2" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_2" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
       <Group key="b0162966-0060-4af5-82d1-fcb491ad7619/be0a0e37-ad17-42ca-b5a1-1a654d736358">
         <Data key="check_tolerance" value="True" />
         <Data key="clock_version" value="v1" />
@@ -216,6 +454,30 @@
         <Data key="sync_with_bus_clk" value="True" />
         <Data key="user_set_domain" value="False" />
       </Group>
+      <Group key="b722443b-8f81-46dc-bf9b-c95eb62bc181">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_1" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_1" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
       <Group key="cb7e877c-9fb4-4fc1-a708-f1e48eb5a68c">
         <Data key="check_tolerance" value="True" />
         <Data key="clock_version" value="v1" />
@@ -240,6 +502,30 @@
         <Data key="sync_with_bus_clk" value="True" />
         <Data key="user_set_domain" value="False" />
       </Group>
+      <Group key="d3075dc6-05c8-4dc9-9959-cf7014c0e66f">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_7" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_7" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
       <Group key="e4a53a4c-40e1-4747-a72a-10193ffdf31c">
         <Data key="check_tolerance" value="True" />
         <Data key="clock_version" value="v1" />
@@ -537,15 +823,27 @@
   <Group key="DWRInstGuidMapping">
     <Group key="Clock">
       <Data key="0b2f9bbb-00ce-4115-a788-ffb9d046a9e5" value="Clock_4" />
+      <Data key="1a7e8637-3b6b-4e84-839c-0dfc18fdaf5b" value="Clock_5" />
+      <Data key="3f3708ae-fb62-4012-919b-9a3b9a1dfbc2" value="Clock_8" />
+      <Data key="4eef02b9-8ad1-43c4-85f1-b3335faa5fc4" value="Clock_3" />
       <Data key="06c4d5d4-f15f-4b29-a1d0-c24b2e38b1ec" value="CounterClock" />
       <Data key="24cd38f7-f472-4403-837f-86807c8f5333" value="PULSE_CLOCK" />
       <Data key="63ed4137-0b09-4256-8a27-35c9a2653f1a" value="Clock_2" />
       <Data key="66f14071-bddd-4b4d-a9aa-a129cceaa7b6" value="Clock_3" />
+      <Data key="71bc291d-84a7-40a8-b7b2-1c8a34326a31" value="CLOCK300" />
+      <Data key="90ce0c72-9f10-44ef-a049-f0f525d59bea" value="CLOCK8" />
       <Data key="349ffa20-8576-4ac3-9a6f-34ef606de6cf" value="Clock_1" />
+      <Data key="4033c29d-f4bc-4e94-ac95-aa587e869f88/696a0979-21fc-4185-bf38-6c79febcde7a" value="OUTPUT_VOLTAGE_ADC_theACLK" />
       <Data key="6616e828-6611-4893-a674-66c861d79d6c" value="SignalSamplingClock" />
       <Data key="12664fc6-9d70-44b1-8a49-887a292e1b7f" value="Clock_3" />
+      <Data key="75187c05-9501-4450-b306-6ccdd3bb77db" value="Clock_5" />
+      <Data key="09974428-e912-491f-8d2f-361ba50e7599" value="Clock_6" />
+      <Data key="a5825a94-fa18-4e4f-a843-bc687cacbd56/696a0979-21fc-4185-bf38-6c79febcde7a" value="INPUT_VOLTAGE_ADC_theACLK" />
+      <Data key="b762c287-7f87-4b21-982e-84be01dc5115" value="Clock_2" />
       <Data key="b0162966-0060-4af5-82d1-fcb491ad7619/be0a0e37-ad17-42ca-b5a1-1a654d736358" value="UART_IntClock" />
+      <Data key="b722443b-8f81-46dc-bf9b-c95eb62bc181" value="Clock_1" />
       <Data key="cb7e877c-9fb4-4fc1-a708-f1e48eb5a68c" value="CounterClock" />
+      <Data key="d3075dc6-05c8-4dc9-9959-cf7014c0e66f" value="Clock_7" />
       <Data key="e4a53a4c-40e1-4747-a72a-10193ffdf31c" value="Clock_1" />
       <Data key="efd5f185-0c32-4824-ba72-3ceb5356f5a7" value="Clock_1" />
     </Group>
@@ -553,6 +851,7 @@
       <Data key="4a398466-709f-4228-9500-96178658e13e" value="RDATA" />
       <Data key="5a3407c1-b434-4438-a7b4-b9dfd2280495" value="MOTEA" />
       <Data key="8d318d8b-cf7b-4b6b-b02c-ab1c5c49d0ba" value="SW1" />
+      <Data key="12e00eac-69b5-4717-85c8-25ef6b224d4c" value="DEBUG_PINS" />
       <Data key="41e2d8ed-5494-4d8c-8ff7-f4f789cece51" value="REDWC" />
       <Data key="264be2d3-9481-494b-8d9c-c1905a45e9cc" value="FDD" />
       <Data key="472f8fdb-f772-44fb-8897-cc690694237b" value="WDATA" />
@@ -561,17 +860,20 @@
       <Data key="1425177d-0d0e-4468-8bcc-e638e5509a9b" value="UartRx" />
       <Data key="a5d987c6-e45b-45b9-ad93-656fab06d720" value="TRK00" />
       <Data key="a93ef5b3-00f4-42c0-8fad-0e275a7e2537" value="MOTEB" />
+      <Data key="b8380fb7-fdb8-449f-bd8d-c4ca96cdf55a" value="DEBUG_PINS" />
+      <Data key="bc2e8987-db82-469c-bf6f-22fd3464cc70" value="DEBUG_PINS" />
       <Data key="bc5d52a1-1b25-4aa0-9ba9-3f81d122772f" value="DEBUG_PINS" />
       <Data key="beca5e2d-f70f-4900-a4db-7eca1ed3126e/8b77a6c4-10a0-4390-971c-672353e2a49c" value="USBFS_Dm" />
       <Data key="beca5e2d-f70f-4900-a4db-7eca1ed3126e/618a72fc-5ddd-4df5-958f-a3d55102db42" value="USBFS_Dp" />
       <Data key="c5367cde-21d5-4866-9a32-d16abfea0c61" value="WPT" />
       <Data key="d19368c5-6855-41bb-a9ff-808938abef00" value="INDEX" />
       <Data key="e9f14b5a-b2bf-49b8-98f3-d7b5a43ace8d" value="DRVSB" />
-      <Data key="e851a3b9-efb8-48be-bbb8-b303b216c393" value="LED" />
+      <Data key="e851a3b9-efb8-48be-bbb8-b303b216c393" value="INDEX300" />
       <Data key="e51063a9-4fad-40c7-a06b-7cc4b137dc18" value="DSKCHG" />
       <Data key="ea7ee228-8b3f-426c-8bb8-cd7a81937769" value="DIR" />
       <Data key="ed092b9b-d398-4703-be89-cebf998501f6" value="UartTx" />
-      <Data key="fbd1f839-40f9-498e-a48b-5f3048ea5c3d/52f31aa9-2f0a-497d-9a1f-1424095e13e6" value="SW_Tx_UART_1_tx" />
+      <Data key="f9a7371a-8a7d-4144-8b08-69e3d2a3a663" value="INDEX360" />
+      <Data key="fbd1f839-40f9-498e-a48b-5f3048ea5c3d/52f31aa9-2f0a-497d-9a1f-1424095e13e6" value="UART_tx" />
       <Data key="fede1767-f3fd-4021-b3d7-8f9d88f36f9b" value="DRVSA" />
       <Data key="fff78075-035e-43d7-8577-bc5be4d21926" value="WGATE" />
     </Group>
@@ -3675,6 +3977,20 @@
         <Data key="Port Format" value="2,2" />
       </Group>
     </Group>
+    <Group key="12e00eac-69b5-4717-85c8-25ef6b224d4c">
+      <Group key="0">
+        <Data key="Port Format" value="2,2" />
+      </Group>
+      <Group key="1">
+        <Data key="Port Format" value="2,3" />
+      </Group>
+      <Group key="2">
+        <Data key="Port Format" value="2,4" />
+      </Group>
+      <Group key="3">
+        <Data key="Port Format" value="2,0" />
+      </Group>
+    </Group>
     <Group key="41e2d8ed-5494-4d8c-8ff7-f4f789cece51">
       <Group key="0">
         <Data key="Port Format" value="2,7" />
@@ -3757,6 +4073,43 @@
         <Data key="Port Format" value="12,1" />
       </Group>
     </Group>
+    <Group key="b8380fb7-fdb8-449f-bd8d-c4ca96cdf55a">
+      <Group key="0">
+        <Data key="Port Format" value="2,5" />
+      </Group>
+      <Group key="1">
+        <Data key="Port Format" value="2,4" />
+      </Group>
+      <Group key="2">
+        <Data key="Port Format" value="2,3" />
+      </Group>
+    </Group>
+    <Group key="bc2e8987-db82-469c-bf6f-22fd3464cc70">
+      <Group key="0">
+        <Data key="Port Format" value="0,0" />
+      </Group>
+      <Group key="1">
+        <Data key="Port Format" value="0,1" />
+      </Group>
+      <Group key="2">
+        <Data key="Port Format" value="0,2" />
+      </Group>
+      <Group key="3">
+        <Data key="Port Format" value="0,3" />
+      </Group>
+      <Group key="4">
+        <Data key="Port Format" value="0,4" />
+      </Group>
+      <Group key="5">
+        <Data key="Port Format" value="0,5" />
+      </Group>
+      <Group key="6">
+        <Data key="Port Format" value="0,6" />
+      </Group>
+      <Group key="7">
+        <Data key="Port Format" value="0,7" />
+      </Group>
+    </Group>
     <Group key="bc5d52a1-1b25-4aa0-9ba9-3f81d122772f">
       <Group key="0">
         <Data key="Port Format" value="0,5" />
@@ -3792,7 +4145,7 @@
     </Group>
     <Group key="e851a3b9-efb8-48be-bbb8-b303b216c393">
       <Group key="0">
-        <Data key="Port Format" value="2,1" />
+        <Data key="Port Format" value="3,0" />
       </Group>
     </Group>
     <Group key="e51063a9-4fad-40c7-a06b-7cc4b137dc18">
@@ -3810,9 +4163,14 @@
         <Data key="Port Format" value="12,7" />
       </Group>
     </Group>
+    <Group key="f9a7371a-8a7d-4144-8b08-69e3d2a3a663">
+      <Group key="0">
+        <Data key="Port Format" value="3,1" />
+      </Group>
+    </Group>
     <Group key="fbd1f839-40f9-498e-a48b-5f3048ea5c3d/52f31aa9-2f0a-497d-9a1f-1424095e13e6">
       <Group key="0">
-        <Data key="Port Format" value="2,0" />
+        <Data key="Port Format" value="12,7" />
       </Group>
     </Group>
     <Group key="fede1767-f3fd-4021-b3d7-8f9d88f36f9b">
@@ -3840,7 +4198,7 @@
     <Data key="CYDEV_ECC_ENABLE" value="False" />
     <Data key="CYDEV_HEAP_SIZE" value="0x80" />
     <Data key="CYDEV_INSTRUCT_CACHE_ENABLED" value="True" />
-    <Data key="CYDEV_PROTECTION_ENABLE" value="False" />
+    <Data key="CYDEV_PROTECTION_ENABLE" value="True" />
     <Data key="CYDEV_STACK_SIZE" value="0x0800" />
     <Data key="CYDEV_TEMPERATURE" value="0C - 85/125C" />
     <Data key="CYDEV_TRACE_ENABLED" value="False" />

FluxEngine.cydsn/Sampler/Sampler.v

@@ -0,0 +1,134 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+`include "../SuperCounter/SuperCounter.v"
+
+//`#end` -- edit above this line, do not edit this line
+// Generated on 12/11/2019 at 21:18
+// Component: Sampler
+module Sampler (
+	output [2:0] debug_state,
+	output reg [7:0] opcode,
+	output  req,
+	input   clock,
+	input   index,
+	input   rdata,
+	input   reset,
+	input   sampleclock
+);
+
+//`#start body` -- edit after this line, do not edit this line
+
+localparam STATE_RESET = 0;
+localparam STATE_WAITING = 1;
+localparam STATE_INTERVAL = 2;
+localparam STATE_DISPATCH = 3;
+localparam STATE_OPCODE = 4;
+localparam STATE_COUNTING = 5;
+
+reg [2:0] state;
+wire [6:0] counter;
+
+wire countnow;
+assign countnow = (state == STATE_COUNTING);
+
+wire counterreset;
+assign counterreset = (state == STATE_INTERVAL) || (state == STATE_OPCODE);
+
+SuperCounter #(.Delta(1), .ResetValue(0)) Counter
+(
+    /* input */ .clk(clock),
+    /* input */ .reset(counterreset),
+    /* input */ .count(countnow),
+    /* output */ .d(counter)
+);
+
+reg oldsampleclock;
+wire sampleclocked;
+assign sampleclocked = !oldsampleclock && sampleclock;
+
+reg oldindex;
+wire indexed;
+assign indexed = !oldindex && index;
+
+wire rdataed;
+reg oldrdata;
+assign rdataed = !oldrdata && rdata;
+
+assign req = (state == STATE_INTERVAL) || (state == STATE_OPCODE);
+
+always @(posedge clock)
+begin
+    if (reset)
+    begin
+        state <= STATE_RESET;
+        opcode <= 0;
+        oldsampleclock <= 0;
+        oldindex <= 0;
+        oldrdata <= 0;
+    end
+    else
+        case (state)
+            STATE_RESET:
+                state <= STATE_WAITING;
+            
+            STATE_WAITING:
+            begin
+                if (rdataed || indexed)
+                begin
+                    opcode <= {0, counter};
+                    state <= STATE_INTERVAL;
+                end
+                else if (sampleclocked)
+                begin
+                    oldsampleclock <= 1;
+                    if (counter == 7'h7f)
+                    begin
+                        opcode <= {0, counter};
+                        state <= STATE_OPCODE;
+                    end
+                    else
+                        state <= STATE_COUNTING;
+                end
+                
+                if (oldrdata && !rdata)
+                    oldrdata <= 0;
+                if (oldindex && !index)
+                    oldindex <= 0;
+                if (oldsampleclock && !sampleclock)
+                    oldsampleclock <= 0;
+            end
+            
+            STATE_INTERVAL: /* interval byte sent here; counter reset */
+                state <= STATE_DISPATCH;
+                
+            STATE_DISPATCH: /* relax after interval byte, dispatch for opcode */
+            begin
+                if (rdataed)
+                begin
+                    oldrdata <= 1;
+                    opcode <= 8'h80;
+                    state <= STATE_OPCODE;
+                end
+                else if (indexed)
+                begin
+                    oldindex <= 1;
+                    opcode <= 8'h81;
+                    state <= STATE_OPCODE;
+                end
+                else
+                    state <= STATE_WAITING;
+            end
+            
+            STATE_OPCODE: /* opcode byte sent here */
+                state <= STATE_WAITING;
+                            
+            STATE_COUNTING:
+                state <= STATE_WAITING;
+        endcase
+end
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line

FluxEngine.cydsn/Sequencer/Sequencer.v

@@ -0,0 +1,103 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+// Generated on 11/24/2019 at 17:25
+// Component: Sequencer
+module Sequencer (
+	output req, /* request new data on leading edge */
+	output wdata,
+    output [2:0] debug_state,
+	input clock,
+	input dataclock, /* incoming data on leading edge */
+	input [7:0] opcode,
+    input index,
+    input sampleclock,
+    input reset
+);
+
+//`#start body` -- edit after this line, do not edit this line
+
+localparam STATE_IDLE = 0;
+localparam STATE_LOAD = 1;
+localparam STATE_WAITING = 2;
+localparam STATE_PULSING = 3;
+localparam STATE_INDEXING = 4;
+
+localparam OPCODE_PULSE = 8'h80;
+localparam OPCODE_INDEX = 8'h81;
+
+reg [2:0] state;
+reg [6:0] countdown;
+
+assign req = (state == STATE_LOAD);
+assign wdata = (state == STATE_PULSING);
+assign debug_state = state;
+
+reg olddataclock;
+wire dataclocked;
+always @(posedge clock) olddataclock <= dataclock;
+assign dataclocked = !olddataclock && dataclock;
+
+reg oldsampleclock;
+wire sampleclocked;
+always @(posedge clock) oldsampleclock <= sampleclock;
+assign sampleclocked = !oldsampleclock && sampleclock;
+
+reg oldindex;
+wire indexed;
+always @(posedge clock) oldindex <= index;
+assign indexed = !oldindex && index;
+
+always @(posedge clock)
+begin
+    if (reset)
+    begin
+        state <= STATE_IDLE;
+        countdown <= 0;
+    end
+    else
+        case (state)
+            STATE_IDLE:
+                state <= STATE_LOAD;
+            
+            STATE_LOAD:
+                if (dataclocked)
+                    case (opcode)
+                        OPCODE_PULSE:
+                            state <= STATE_PULSING;
+                        
+                        OPCODE_INDEX:
+                            state <= STATE_INDEXING;
+                        
+                        default:
+                        begin
+                            countdown <= opcode[6:0];
+                            state <= STATE_WAITING;
+                        end
+                    endcase
+            
+            STATE_WAITING:
+                if (sampleclocked)
+                begin
+                    if (countdown == 0)
+                        state <= STATE_LOAD;
+                    else
+                        countdown <= countdown - 1;
+                end
+            
+            STATE_PULSING:
+                state <= STATE_LOAD;
+            
+            STATE_INDEXING:
+                if (indexed)
+                    state <= STATE_LOAD;
+                else
+                    state <= STATE_INDEXING;
+        endcase
+end
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line

FluxEngine.cydsn/SuperCounter/SuperCounter.v

@@ -0,0 +1,156 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+// Generated on 11/16/2017 at 15:44
+// Component: FIFOout
+module SuperCounter (
+	input clk,
+    input reset,
+    input count,
+    output [7:0] d,
+	output drq,
+	output empty,
+    output ack
+);
+
+//`#start body` -- edit after this line, do not edit this line
+
+parameter ResetValue = 0;
+parameter Delta = 1;
+    
+wire [7:0] po;
+assign d = po;
+
+localparam STATE_RESET = 0;
+localparam STATE_WAIT = 1;
+localparam STATE_ADD = 2;
+
+reg oldcount;
+wire counted;
+assign counted = count && !oldcount;
+
+always @(posedge clk) oldcount <= count;
+
+wire [2:0] cs;
+assign cs = reset ? STATE_RESET : (counted ? STATE_ADD : STATE_WAIT);
+            
+cy_psoc3_dp #(.d0_init(ResetValue), .d1_init(Delta), 
+.cy_dpconfig(
+{
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM0:  STATE_RESET*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM1:  STATE_WAIT*/
+    `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D1,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM2:  STATE_ADD*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM3:             */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM4:             */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM5:             */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM6:             */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM7:             */
+    8'hFF, 8'h00,  /*CFG9:             */
+    8'hFF, 8'hFF,  /*CFG11-10:             */
+    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
+    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
+    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
+    `SC_SI_A_DEFSI, /*CFG13-12:             */
+    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
+    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
+    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
+    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
+    `SC_CMP0_NOCHN, /*CFG15-14:             */
+    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
+    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
+    `SC_WRK16CAT_DSBL /*CFG17-16:             */
+}
+)) dp(
+        /*  input                   */  .reset(1'b0),
+        /*  input                   */  .clk(clk),
+        /*  input   [02:00]         */  .cs_addr(cs),
+        /*  input                   */  .route_si(1'b0),
+        /*  input                   */  .route_ci(1'b0),
+        /*  input                   */  .f0_load(1'b0),
+        /*  input                   */  .f1_load(1'b0),
+        /*  input                   */  .d0_load(1'b0),
+        /*  input                   */  .d1_load(1'b0),
+        /*  output                  */  .ce0(),
+        /*  output                  */  .cl0(),
+        /*  output                  */  .z0(),
+        /*  output                  */  .ff0(),
+        /*  output                  */  .ce1(),
+        /*  output                  */  .cl1(),
+        /*  output                  */  .z1(),
+        /*  output                  */  .ff1(),
+        /*  output                  */  .ov_msb(),
+        /*  output                  */  .co_msb(),
+        /*  output                  */  .cmsb(),
+        /*  output                  */  .so(),
+        /*  output                  */  .f0_bus_stat(),
+        /*  output                  */  .f0_blk_stat(),
+        /*  output                  */  .f1_bus_stat(),
+        /*  output                  */  .f1_blk_stat(),
+        
+        /* input                    */  .ci(1'b0),     // Carry in from previous stage
+        /* output                   */  .co(),// Carry out to next stage
+        /* input                    */  .sir(1'b0),    // Shift in from right side
+        /* output                   */  .sor(),        // Shift out to right side
+        /* input                    */  .sil(1'b0),    // Shift in from left side
+        /* output                   */  .sol(),        // Shift out to left side
+        /* input                    */  .msbi(1'b0),   // MSB chain in
+        /* output                   */  .msbo(),       // MSB chain out
+        /* input [01:00]            */  .cei(2'b0),    // Compare equal in from prev stage
+        /* output [01:00]           */  .ceo(),        // Compare equal out to next stage
+        /* input [01:00]            */  .cli(2'b0),    // Compare less than in from prv stage
+        /* output [01:00]           */  .clo(),        // Compare less than out to next stage
+        /* input [01:00]            */  .zi(2'b0),     // Zero detect in from previous stage
+        /* output [01:00]           */  .zo(),         // Zero detect out to next stage
+        /* input [01:00]            */  .fi(2'b0),     // 0xFF detect in from previous stage
+        /* output [01:00]           */  .fo(),         // 0xFF detect out to next stage
+        /* input [01:00]            */  .capi(2'b0),   // Software capture from previous stage
+        /* output [01:00]           */  .capo(),       // Software capture to next stage
+        /* input                    */  .cfbi(1'b0),   // CRC Feedback in from previous stage
+        /* output                   */  .cfbo(),       // CRC Feedback out to next stage
+        /* input [07:00]            */  .pi(8'b0),     // Parallel data port
+        /* output [07:00]           */  .po(po)       // Parallel data port
+);
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
+
+
+
+
+
+
+
+
+
+
+
+
+
+

FluxEngine.cydsn/main.c

@@ -85,10 +85,21 @@ static void print(const char* msg, ...)
     UART_PutCRLF();
 }
 
+static void set_drive_flags(uint8_t flags)
+{
+    if (current_drive_flags != flags)
+        homed = false;
+    
+    current_drive_flags = flags;
+    DRIVESELECT_REG_Write((flags & 1) ? 2 : 1); /* select drive 1 or 0 */
+    DENSITY_REG_Write(flags >> 1); /* density bit */
+}
+
 static void start_motor(void)
 {
     if (!motor_on)
     {
+        set_drive_flags(current_drive_flags);
         MOTOR_REG_Write(1);
         CyDelay(1000);
         homed = false;
@@ -99,6 +110,16 @@ static void start_motor(void)
     CyWdtClear();
 }
 
+static void stop_motor(void)
+{
+    if (motor_on)
+    {
+        MOTOR_REG_Write(0);
+        DRIVESELECT_REG_Write(0); /* deselect all drives */
+        motor_on = false;
+    }
+}
+
 static void wait_until_writeable(int ep)
 {
     while (USBFS_GetEPState(ep) != USBFS_IN_BUFFER_EMPTY)
@@ -138,25 +159,36 @@ static void cmd_get_version(struct any_frame* f)
 
 static void step(int dir)
 {
-    STEP_REG_Write(dir);
-    CyDelayUs(1);
-    STEP_REG_Write(dir | 2);
-    CyDelayUs(1);
-    STEP_REG_Write(dir);
+    STEP_REG_Write(dir); /* step high */
+    CyDelayUs(6);
+    STEP_REG_Write(dir | 2); /* step low */
+    CyDelayUs(6);
+    STEP_REG_Write(dir); /* step high again, drive moves now */
     CyDelay(STEP_INTERVAL_TIME);
 }
 
+static void home(void)
+{
+    for (int i=0; i<100; i++)
+    {
+        /* Don't keep stepping forever, because if a drive's
+         * not connected bad things happen. */
+        if (TRACK0_REG_Read())
+            break;
+        step(STEP_TOWARDS0);
+    }
+    
+    /* Step to -1, which should be a nop, to reset the disk on disk change. */
+    step(STEP_TOWARDS0);
+}
+
 static void seek_to(int track)
 {
     start_motor();
-    if (!homed)
+    if (!homed || (track == 0))
     {
         print("homing");
-        while (!TRACK0_REG_Read())
-            step(STEP_TOWARDS0);
-            
-        /* Step to -1, which should be a nop, to reset the disk on disk change. */
-        step(STEP_TOWARDS0);
+        home();
         
         homed = true;
         current_track = 0;
@@ -167,11 +199,7 @@ static void seek_to(int track)
     while (track != current_track)
     {
         if (TRACK0_REG_Read())
-        {
-            if (current_track != 0)
-                print("unexpectedly detected track 0");
             current_track = 0;
-        }
         
         if (track > current_track)
         {
@@ -249,7 +277,7 @@ static void deinit_dma(void)
 
 static void init_capture_dma(void)
 {
-    dma_channel = CAPTURE_DMA_DmaInitialize(
+    dma_channel = SAMPLER_DMA_DmaInitialize(
         2 /* bytes */,
         true /* request per burst */, 
         HI16(CYDEV_PERIPH_BASE),
@@ -264,8 +292,8 @@ static void init_capture_dma(void)
             nexti = 0;
 
         CyDmaTdSetConfiguration(td[i], BUFFER_SIZE, td[nexti],   
-            CY_DMA_TD_INC_DST_ADR | CAPTURE_DMA__TD_TERMOUT_EN);
-        CyDmaTdSetAddress(td[i], LO16((uint32)&SAMPLER_DATAPATH_F0_REG), LO16((uint32)&dma_buffer[i]));
+            CY_DMA_TD_INC_DST_ADR | SAMPLER_DMA__TD_TERMOUT_EN);
+        CyDmaTdSetAddress(td[i], LO16((uint32)SAMPLER_FIFO_FIFO_PTR), LO16((uint32)&dma_buffer[i]));
     }    
 }
 
@@ -276,13 +304,11 @@ static void cmd_read(struct read_frame* f)
     
     /* Do slow setup *before* we go into the real-time bit. */
     
-    SAMPLER_CONTROL_Write(1); /* reset */
-    
     {
         uint8_t i = CyEnterCriticalSection();
-        SAMPLER_DATAPATH_F0_SET_LEVEL_MID;
-        SAMPLER_DATAPATH_F0_CLEAR;
-        SAMPLER_DATAPATH_F0_SINGLE_BUFFER_UNSET;
+        SAMPLER_FIFO_SET_LEVEL_MID;
+        SAMPLER_FIFO_CLEAR;
+        SAMPLER_FIFO_SINGLE_BUFFER_UNSET;
         CyExitCriticalSection(i);
     }
     
@@ -291,7 +317,6 @@ static void cmd_read(struct read_frame* f)
 
     /* Wait for the beginning of a rotation. */
         
-    print("wait");
     index_irq = false;
     while (!index_irq)
         ;
@@ -305,7 +330,6 @@ static void cmd_read(struct read_frame* f)
     dma_reading_from_td = -1;
     dma_underrun = false;
     int count = 0;
-    SAMPLER_CONTROL_Write(0); /* !reset */
     CyDmaChSetInitialTd(dma_channel, td[dma_writing_to_td]);
     CyDmaClearPendingDrq(dma_channel);
     CyDmaChEnable(dma_channel, 1);
@@ -364,19 +388,21 @@ static void cmd_read(struct read_frame* f)
         }
         dma_reading_from_td = NEXT_BUFFER(dma_reading_from_td);
     }
-abort:
+abort:;
     CyDmaChSetRequest(dma_channel, CY_DMA_CPU_TERM_CHAIN);
     while (CyDmaChGetRequest(dma_channel))
         ;
 
     donecrunch(&cs);
     wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
-    unsigned zz = cs.outputlen;
-    if (cs.outputlen != BUFFER_SIZE)
-        USBFS_LoadInEP(FLUXENGINE_DATA_IN_EP_NUM, usb_buffer, BUFFER_SIZE-cs.outputlen);
+    if (!dma_underrun)
+    {
+        if (cs.outputlen != BUFFER_SIZE)
+            USBFS_LoadInEP(FLUXENGINE_DATA_IN_EP_NUM, usb_buffer, BUFFER_SIZE-cs.outputlen);
+        wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
+    }
     if ((cs.outputlen == BUFFER_SIZE) || (cs.outputlen == 0))
         USBFS_LoadInEP(FLUXENGINE_DATA_IN_EP_NUM, NULL, 0);
-    wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
     deinit_dma();
 
     if (dma_underrun)
@@ -389,7 +415,7 @@ abort:
         DECLARE_REPLY_FRAME(struct any_frame, F_FRAME_READ_REPLY);
         send_reply(&r);
     }
-    print("count=%d i=%d d=%d zz=%d", count, index_irq, dma_underrun, zz);
+    print("count=%d i=%d d=%d", count, index_irq, dma_underrun);
 }
 
 static void init_replay_dma(void)
@@ -410,25 +436,28 @@ static void init_replay_dma(void)
 
         CyDmaTdSetConfiguration(td[i], BUFFER_SIZE, td[nexti],
             CY_DMA_TD_INC_SRC_ADR | SEQUENCER_DMA__TD_TERMOUT_EN);
-        CyDmaTdSetAddress(td[i], LO16((uint32)&dma_buffer[i]), LO16((uint32)&SEQUENCER_DATAPATH_F0_REG));
+        CyDmaTdSetAddress(td[i], LO16((uint32)&dma_buffer[i]), LO16((uint32)REPLAY_FIFO_FIFO_PTR));
     }    
 }
 
 static void cmd_write(struct write_frame* f)
 {
+    print("cmd_write");
+    
     if (f->bytes_to_write % FRAME_SIZE)
     {
         send_error(F_ERROR_INVALID_VALUE);
         return;
     }
     
+    SEQUENCER_CONTROL_Write(1); /* put the sequencer into reset */
+
     SIDE_REG_Write(f->side);
-    SEQUENCER_CONTROL_Write(1); /* reset */
     {
-        uint8_t i = CyEnterCriticalSection();
-        SEQUENCER_DATAPATH_F0_SET_LEVEL_NORMAL;
-        SEQUENCER_DATAPATH_F0_CLEAR;
-        SEQUENCER_DATAPATH_F0_SINGLE_BUFFER_UNSET;
+        uint8_t i = CyEnterCriticalSection();        
+        REPLAY_FIFO_SET_LEVEL_NORMAL;
+        REPLAY_FIFO_CLEAR;
+        REPLAY_FIFO_SINGLE_BUFFER_UNSET;
         CyExitCriticalSection(i);
     }
     seek_to(current_track);    
@@ -553,7 +582,7 @@ abort:
         CyDmaChDisable(dma_channel);
     }
     
-    //debug("p=%d cr=%d cw=%d f=%d l=%d w=%d index=%d underrun=%d", packets, count_read, count_written, finished, listening, writing, index_irq, dma_underrun);
+    print("p=%d cr=%d cw=%d f=%d w=%d index=%d underrun=%d", packets, count_read, count_written, finished, writing, index_irq, dma_underrun);
     if (!finished)
     {
         while (count_read < packets)
@@ -571,6 +600,7 @@ abort:
     }
     
     deinit_dma();
+    print("write finished");
     
     if (dma_underrun)
     {
@@ -605,17 +635,101 @@ static void cmd_erase(struct erase_frame* f)
 
 static void cmd_set_drive(struct set_drive_frame* f)
 {
-    if (current_drive_flags != f->drive_flags)
-    {
-        current_drive_flags = f->drive_flags;
-        DRIVE_REG_Write(current_drive_flags);
-        homed = false;
-    }
+    set_drive_flags(f->drive_flags);
     
     DECLARE_REPLY_FRAME(struct any_frame, F_FRAME_SET_DRIVE_REPLY);
     send_reply((struct any_frame*) &r);
 }
-   
+
+static uint16_t read_output_voltage_mv(void)
+{
+    OUTPUT_VOLTAGE_ADC_StartConvert();
+    OUTPUT_VOLTAGE_ADC_IsEndConversion(OUTPUT_VOLTAGE_ADC_WAIT_FOR_RESULT);
+    uint16_t samples = OUTPUT_VOLTAGE_ADC_GetResult16();
+    return OUTPUT_VOLTAGE_ADC_CountsTo_mVolts(samples);
+}
+
+static void read_output_voltages(struct voltages* v)
+{
+    SIDE_REG_Write(1); /* set DIR to low (remember this is inverted) */
+    CyDelay(100);
+    v->logic0_mv = read_output_voltage_mv();
+
+    SIDE_REG_Write(0);
+    CyDelay(100);
+    v->logic1_mv = read_output_voltage_mv();
+}
+
+static uint16_t read_input_voltage_mv(void)
+{
+    INPUT_VOLTAGE_ADC_StartConvert();
+    INPUT_VOLTAGE_ADC_IsEndConversion(INPUT_VOLTAGE_ADC_WAIT_FOR_RESULT);
+    uint16_t samples = INPUT_VOLTAGE_ADC_GetResult16();
+    return INPUT_VOLTAGE_ADC_CountsTo_mVolts(samples);
+}
+
+static void read_input_voltages(struct voltages* v)
+{
+    home();
+    CyDelay(50);
+    v->logic0_mv = read_input_voltage_mv();
+    
+    step(STEP_AWAYFROM0);
+    CyDelay(50);
+    v->logic1_mv = read_input_voltage_mv();
+}
+
+static void cmd_measure_voltages(void)
+{
+    stop_motor();
+    INPUT_VOLTAGE_ADC_Start();
+    INPUT_VOLTAGE_ADC_SetPower(INPUT_VOLTAGE_ADC__HIGHPOWER);
+    OUTPUT_VOLTAGE_ADC_Start();
+    OUTPUT_VOLTAGE_ADC_SetPower(OUTPUT_VOLTAGE_ADC__HIGHPOWER);
+    
+    DECLARE_REPLY_FRAME(struct voltages_frame, F_FRAME_MEASURE_VOLTAGES_REPLY);
+    
+    CyWdtClear();
+    MOTOR_REG_Write(0); /* should be ignored anyway */
+    DRIVESELECT_REG_Write(0); /* deselect both drives */
+    CyDelay(200); /* wait for things to settle */
+    read_output_voltages(&r.output_both_off);
+    read_input_voltages(&r.input_both_off);
+
+    CyWdtClear();
+    DRIVESELECT_REG_Write(1); /* select drive 0 */
+    CyDelay(50);
+    read_output_voltages(&r.output_drive_0_selected);
+    read_input_voltages(&r.input_drive_0_selected);
+    MOTOR_REG_Write(1);
+    CyDelay(300);
+    CyWdtClear();
+    read_output_voltages(&r.output_drive_0_running);
+    read_input_voltages(&r.input_drive_0_running);
+    MOTOR_REG_Write(0);
+    CyDelay(300);
+    
+    CyWdtClear();
+    DRIVESELECT_REG_Write(2); /* select drive 1 */
+    CyDelay(50);
+    read_output_voltages(&r.output_drive_1_selected);
+    read_input_voltages(&r.input_drive_1_selected);
+    MOTOR_REG_Write(1);
+    CyDelay(300);
+    CyWdtClear();
+    read_output_voltages(&r.output_drive_1_running);
+    read_input_voltages(&r.input_drive_1_running);
+    MOTOR_REG_Write(0);
+    CyDelay(300);
+
+    CyWdtClear();
+    DRIVESELECT_REG_Write(0);
+    homed = false;
+    INPUT_VOLTAGE_ADC_Stop();
+    OUTPUT_VOLTAGE_ADC_Stop();
+    send_reply((struct any_frame*) &r);
+}
+
 static void handle_command(void)
 {
     static uint8_t input_buffer[FRAME_SIZE];
@@ -660,6 +774,10 @@ static void handle_command(void)
         case F_FRAME_SET_DRIVE_CMD:
             cmd_set_drive((struct set_drive_frame*) f);
             break;
+        
+        case F_FRAME_MEASURE_VOLTAGES_CMD:
+            cmd_measure_voltages();
+            break;
             
         default:
             send_error(F_ERROR_BAD_COMMAND);
@@ -672,9 +790,11 @@ int main(void)
     CySysTickStart();
     CySysTickSetCallback(4, system_timer_cb);
     INDEX_IRQ_StartEx(&index_irq_cb);
-    CAPTURE_DMA_FINISHED_IRQ_StartEx(&capture_dma_finished_irq_cb);
+    SAMPLER_DMA_FINISHED_IRQ_StartEx(&capture_dma_finished_irq_cb);
     SEQUENCER_DMA_FINISHED_IRQ_StartEx(&replay_dma_finished_irq_cb);
-    DRIVE_REG_Write(0);
+    INPUT_VOLTAGE_ADC_Stop();
+    OUTPUT_VOLTAGE_ADC_Stop();
+    DRIVESELECT_REG_Write(0);
     UART_Start();
     USBFS_Start(0, USBFS_DWR_VDDD_OPERATION);
     
@@ -690,10 +810,7 @@ int main(void)
         {
             uint32_t time_on = clock - motor_on_time;
             if (time_on > MOTOR_ON_TIME)
-            {
-                MOTOR_REG_Write(0);
-                motor_on = false;
-            }
+                stop_motor();
         }
         
         if (!USBFS_GetConfiguration() || USBFS_IsConfigurationChanged())
@@ -707,6 +824,7 @@ int main(void)
         
         if (USBFS_GetEPState(FLUXENGINE_CMD_OUT_EP_NUM) == USBFS_OUT_BUFFER_FULL)
         {
+            set_drive_flags(current_drive_flags);
             handle_command();
             USBFS_EnableOutEP(FLUXENGINE_CMD_OUT_EP_NUM);
             print("idle");

Makefile

@@ -1,8 +1,8 @@
 PACKAGES = zlib sqlite3 libusb-1.0
 
-export CFLAGS = -O3 -g --std=c++14 \
+export CFLAGS = -Os -g --std=c++14 \
 	-ffunction-sections -fdata-sections
-export LDFLAGS = -O3
+export LDFLAGS = -Os
 
 ifeq ($(OS), Windows_NT)
 export CXX = /mingw32/bin/g++
@@ -13,6 +13,13 @@ export LDFLAGS +=
 export LIBS = -static -lz -lsqlite3 -lusb-1.0
 export EXTENSION = .exe
 else
+
+packages-exist = $(shell pkg-config --exists $(PACKAGES) && echo yes)
+ifneq ($(packages-exist),yes)
+$(warning These pkg-config packages are installed: $(shell pkg-config --list-all | sort | awk '{print $$1}'))
+$(error You must have these pkg-config packages installed: $(PACKAGES))
+endif
+
 export CXX = g++
 export AR = ar rcs
 export STRIP = strip
@@ -22,7 +29,7 @@ export LIBS = $(shell pkg-config --libs $(PACKAGES))
 export EXTENSION =
 endif
 
-CFLAGS += -Ilib -Idep/fmt
+CFLAGS += -Ilib -Idep/fmt -Iarch
 
 export OBJDIR = .obj
 

README.md

@@ -105,6 +105,7 @@ at least, check the CRC so what data's there is probably good.
 |:-----------------------------------------|:-----:|:------:|-------|
 | [AES Superplus / No Problem](doc/disk-aeslanier.md) |  🦖   | | hard sectors! |
 | [Durango F85](doc/disk-durangof85.md)    |  🦖   |        | 5.25" |
+| [DVK MX](doc/disk-mx.md)                 |  🦖   |        | Soviet PDP-11 clone |
 | [Victor 9000](doc/disk-victor9k.md)      |  🦖   |        | 8-inch        |
 | [Zilog MCZ](doc/disk-zilogmcz.md)        |  🦖   |        | 8-inch _and_ hard sectors |
 {: .datatable }
@@ -189,7 +190,7 @@ Jonathan Müller (`foonathan <https://github.com/foonathan>`) with
 contributions from many other people. It is licensed under the terms of the
 BSD license. Please see the contents of the directory for the full text.
 
-As an exception, `dep/fnmatchemu` contains parts of the OpenBSD C library
+As an exception, `dep/emu` contains parts of the OpenBSD C library
 code, Todd Miller and William A. Rowe (and probably others). It is licensed
 under the terms of the 3-clause BSD license. Please see the contents of the
 directory for the full text. It's been lightly modified by me.

arch/amiga/decoder.cc

@@ -92,6 +92,8 @@ void AmigaDecoder::decodeSectorRecord()
 
     uint32_t wanteddatachecksum = deinterleave(ptr, 4).reader().read_be32();
     uint32_t gotdatachecksum = checksum(rawbytes.slice(62, 1024));
-    _sector->data = deinterleave(ptr, 512);
+
+    _sector->data.clear();
+    _sector->data.writer().append(deinterleave(ptr, 512)).append(recoveryinfo);
     _sector->status = (gotdatachecksum == wanteddatachecksum) ? Sector::OK : Sector::BAD_CHECKSUM;
 }

arch/brother/brother.h

@@ -9,6 +9,9 @@
 #define BROTHER_DATA_RECORD_CHECKSUM     3
 #define BROTHER_DATA_RECORD_ENCODED_SIZE 415
 
+#define BROTHER_TRACKS_PER_DISK          78
+#define BROTHER_SECTORS_PER_TRACK        12
+
 class Sector;
 class Fluxmap;
 
@@ -22,9 +25,15 @@ public:
     void decodeDataRecord();
 };
 
-extern void writeBrotherSectorHeader(std::vector<bool>& bits, unsigned& cursor,
-		int track, int sector);
-extern void writeBrotherSectorData(std::vector<bool>& bits, unsigned& cursor,
-		const Bytes& data);
+class BrotherEncoder : public AbstractEncoder
+{
+public:
+	virtual ~BrotherEncoder() {}
+
+public:
+    std::unique_ptr<Fluxmap> encode(int physicalTrack, int physicalSide, const SectorSet& allSectors);
+};
+
+extern FlagGroup brotherEncoderFlags;
 
 #endif

arch/brother/decoder.cc

@@ -3,6 +3,7 @@
 #include "fluxmap.h"
 #include "decoders/fluxmapreader.h"
 #include "decoders/decoders.h"
+#include "encoders/encoders.h"
 #include "record.h"
 #include "brother.h"
 #include "sector.h"

arch/brother/encoder.cc

@@ -0,0 +1,167 @@
+#include "globals.h"
+#include "record.h"
+#include "decoders/decoders.h"
+#include "encoders/encoders.h"
+#include "brother.h"
+#include "crc.h"
+#include "sectorset.h"
+#include "writer.h"
+
+FlagGroup brotherEncoderFlags;
+
+static DoubleFlag clockRateUs(
+	{ "--clock-rate" },
+	"Encoded data clock rate (microseconds).",
+	3.83);
+
+static DoubleFlag postIndexGapMs(
+	{ "--post-index-gap" },
+	"Post-index gap before first sector header (milliseconds).",
+	1.0);
+
+static DoubleFlag sectorSpacingMs(
+	{ "--sector-spacing" },
+	"Time between successive sector headers (milliseconds).",
+	16.2);
+
+static DoubleFlag postHeaderSpacingMs(
+	{ "--post-header-spacing" },
+	"Time between a sector's header and data records (milliseconds).",
+	0.69);
+
+static StringFlag sectorSkew(
+	{ "--sector-skew" },
+	"Order in which to write sectors.",
+	"05a3816b4927");
+
+static int encode_header_gcr(uint16_t word)
+{
+	switch (word)
+	{
+		#define GCR_ENTRY(gcr, data) \
+			case data: return gcr;
+		#include "header_gcr.h"
+		#undef GCR_ENTRY
+	}                       
+	return -1;             
+};
+
+static int encode_data_gcr(uint8_t data)
+{
+	switch (data)
+	{
+		#define GCR_ENTRY(gcr, data) \
+			case data: return gcr;
+		#include "data_gcr.h"
+		#undef GCR_ENTRY
+	}                       
+	return -1;             
+};
+
+static void write_bits(std::vector<bool>& bits, unsigned& cursor, uint32_t data, int width)
+{
+	cursor += width;
+	for (int i=0; i<width; i++)
+	{
+		unsigned pos = cursor - i - 1;
+		if (pos < bits.size())
+			bits[pos] = data & 1;
+		data >>= 1;
+	}
+}
+
+static void write_sector_header(std::vector<bool>& bits, unsigned& cursor,
+		int track, int sector)
+{
+	write_bits(bits, cursor, 0xffffffff, 31);
+	write_bits(bits, cursor, BROTHER_SECTOR_RECORD, 32);
+	write_bits(bits, cursor, encode_header_gcr(track), 16);
+	write_bits(bits, cursor, encode_header_gcr(sector), 16);
+	write_bits(bits, cursor, encode_header_gcr(0x2f), 16);
+}
+
+static void write_sector_data(std::vector<bool>& bits, unsigned& cursor, const Bytes& data)
+{
+	write_bits(bits, cursor, 0xffffffff, 32);
+	write_bits(bits, cursor, BROTHER_DATA_RECORD, 32);
+
+	uint16_t fifo = 0;
+	int width = 0;
+
+	if (data.size() != BROTHER_DATA_RECORD_PAYLOAD)
+		Error() << "unsupported sector size";
+
+	auto write_byte = [&](uint8_t byte)
+	{
+		fifo |= (byte << (8 - width));
+		width += 8;
+
+		while (width >= 5)
+		{
+			uint8_t quintet = fifo >> 11;
+			fifo <<= 5;
+			width -= 5;
+
+			write_bits(bits, cursor, encode_data_gcr(quintet), 8);
+		}
+	};
+
+	for (uint8_t byte : data)
+		write_byte(byte);
+
+	uint32_t realCrc = crcbrother(data);
+	write_byte(realCrc>>16);
+	write_byte(realCrc>>8);
+	write_byte(realCrc);
+	write_byte(0x58); /* magic */
+    write_byte(0xd4);
+    while (width != 0)
+        write_byte(0);
+}
+
+static int charToInt(char c)
+{
+	if (isdigit(c))
+		return c - '0';
+	return 10 + tolower(c) - 'a';
+}
+
+std::unique_ptr<Fluxmap> BrotherEncoder::encode(
+	int physicalTrack, int physicalSide, const SectorSet& allSectors)
+{
+	if ((physicalTrack < 0) || (physicalTrack >= BROTHER_TRACKS_PER_DISK)
+        || (physicalSide != 0))
+		return std::unique_ptr<Fluxmap>();
+
+	int bitsPerRevolution = 200000.0 / clockRateUs;
+	const std::string& skew = sectorSkew.get();
+	std::vector<bool> bits(bitsPerRevolution);
+	unsigned cursor = 0;
+
+	for (int sectorCount=0; sectorCount<BROTHER_SECTORS_PER_TRACK; sectorCount++)
+	{
+		int sectorId = charToInt(skew.at(sectorCount));
+		double headerMs = postIndexGapMs + sectorCount*sectorSpacingMs;
+		unsigned headerCursor = headerMs*1e3 / clockRateUs;
+		double dataMs = headerMs + postHeaderSpacingMs;
+		unsigned dataCursor = dataMs*1e3 / clockRateUs;
+
+		const auto& sectorData = allSectors.get(physicalTrack, 0, sectorId);
+
+		fillBitmapTo(bits, cursor, headerCursor, { true, false });
+		write_sector_header(bits, cursor, physicalTrack, sectorId);
+		fillBitmapTo(bits, cursor, dataCursor, { true, false });
+		write_sector_data(bits, cursor, sectorData->data);
+	}
+
+	if (cursor > bits.size())
+		Error() << "track data overrun";
+	fillBitmapTo(bits, cursor, bits.size(), { true, false });
+
+	// The pre-index gap is not normally reported.
+	// std::cerr << "pre-index gap " << 200.0 - (double)cursor*clockRateUs/1e3 << std::endl;
+	
+	std::unique_ptr<Fluxmap> fluxmap(new Fluxmap);
+	fluxmap->appendBits(bits, clockRateUs*1e3);
+	return fluxmap;
+}

arch/ibm/decoder.cc

@@ -134,6 +134,9 @@ void IbmDecoder::decodeSectorRecord()
     uint16_t gotCrc = crc16(CCITT_POLY, bytes.slice(0, _currentHeaderLength + 5));
     if (wantCrc == gotCrc)
         _sector->status = Sector::DATA_MISSING; /* correct but unintuitive */
+
+    if (_ignoreSideByte)
+        _sector->logicalSide = _sector->physicalSide;
 }
 
 void IbmDecoder::decodeDataRecord()

arch/ibm/ibm.h

@@ -31,8 +31,9 @@ struct IbmIdam
 class IbmDecoder : public AbstractDecoder
 {
 public:
-    IbmDecoder(unsigned sectorBase):
-        _sectorBase(sectorBase)
+    IbmDecoder(unsigned sectorBase, bool ignoreSideByte=false):
+        _sectorBase(sectorBase),
+        _ignoreSideByte(ignoreSideByte)
     {}
 
     RecordType advanceToNextRecord();
@@ -41,6 +42,7 @@ public:
 
 private:
     unsigned _sectorBase;
+    bool _ignoreSideByte;
     unsigned _currentSectorSize;
     unsigned _currentHeaderLength;
 };

arch/macintosh/decoder.cc

@@ -153,6 +153,9 @@ void MacintoshDecoder::decodeSectorRecord()
     uint8_t formatByte = decode_data_gcr(header[3]);
     uint8_t wantedsum = decode_data_gcr(header[4]);
 
+    if (encodedSector > 11)
+        return;
+
     _sector->logicalTrack = _track->physicalTrack;
     _sector->logicalSide = decode_side(encodedSide);
     _sector->logicalSector = encodedSector;
@@ -177,5 +180,7 @@ void MacintoshDecoder::decodeDataRecord()
         inputbuffer[i] = decode_data_gcr(inputbuffer[i]);
         
     _sector->status = Sector::BAD_CHECKSUM;
-    _sector->data = decode_crazy_data(inputbuffer, _sector->status);
+    Bytes userData = decode_crazy_data(inputbuffer, _sector->status);
+    _sector->data.clear();
+    _sector->data.writer().append(userData.slice(12, 512)).append(userData.slice(0, 12));
 }

arch/mx/decoder.cc

@@ -37,7 +37,7 @@ AbstractDecoder::RecordType MxDecoder::advanceToNextRecord()
         const FluxMatcher* matcher = nullptr;
         _sector->clock = _clock = _fmr->seekToPattern(ID_PATTERN, matcher);
         readRawBits(32); /* skip the ID mark */
-        readRawBits(32); /* skip the track number */
+        _logicalTrack = decodeFmMfm(readRawBits(32)).reader().read_be16();
     }
     else if (_currentSector == 10)
     {
@@ -67,7 +67,7 @@ void MxDecoder::decodeSectorRecord()
         gotChecksum += br.read_le16();
     uint16_t wantChecksum = br.read_le16();
 
-    _sector->logicalTrack = _track->physicalTrack;
+    _sector->logicalTrack = _logicalTrack;
     _sector->logicalSide = _track->physicalSide;
     _sector->logicalSector = _currentSector;
     _sector->data = bytes.slice(0, SECTOR_SIZE);

arch/mx/mx.h

@@ -15,6 +15,7 @@ public:
 private:
     nanoseconds_t _clock;
     int _currentSector;
+    int _logicalTrack;
 };
 
 #endif

doc/building.md

@@ -103,7 +103,43 @@ the unconnected pins and solder a short piece of wire to a GND pin on the
 board. Alternatively you'll need to splice it into your drive's power supply
 cable somehow. (The black one.)
 
-## Building the firmware
+## Programming the board
+
+You've got two options here. You can either use the precompiled firmware
+supplied with the source, or else install the Cypress SDK and build it
+yourself. If you want to hack the firmware source you need the latter, but
+if you trust me to do it for you use the precompiled firmware. In either
+case you'll need Windows and have to install some Cypress stuff.
+
+**Before you read this:** If you're on Windows, good news! You can download a
+precompiled version of the FluxEngine client and precompiled firmware [from
+the GitHub releases
+page](https://github.com/davidgiven/fluxengine/releases/latest). Simply unzip
+it somewhere and run the `.exe` files from a `cmd` window (or other shell).
+Follow the instructions below to program the board with the firmware.
+
+### Using the precompiled firmware
+
+On your Windows machine, [install the PSoC
+Programmer](https://www.cypress.com/products/psoc-programming-solutions).
+**Note:** _not_ the Cypress Programmer, which is for a different board!
+Cypress will make you register.
+
+Once done, run it. Plug the blunt end of the FluxEngine board into a USB
+port (the end which is a USB connector). The programmer should detect it
+and report it as a KitProg. You may be prompted to upgrade the programmer
+hardware; if so, follow the instructions and do it.
+
+Now go to File -> File Load and open
+`FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex` in the
+project. If you're on Windows, the precompiled zipfile also contains a copy
+of this file. Press the Program button (the one in the toolbar marked with a
+down arrow). Stuff will happen and you should be left with three green boxes
+in the status bar and 'Programming Succeeded' at the top of the log window.
+
+You're done. You can unplug the board and close the programmer.
+
+### Building the firmware yourself
 
 On your Windows machine, [install the Cypress SDK and CY8CKIT-059
 BSP](http://www.cypress.com/documentation/development-kitsboards/cy8ckit-059-psoc-5lp-prototyping-kit-onboard-programmer-and).
@@ -118,7 +154,7 @@ tutorial and making the LED on your board flash. It'll tell you where all the
 controls are and how to program the board. Remember that the big end of the
 board plugs into your computer for programming.
 
-When you're ready, open the `FluxEngine.cydsn/FluxEngine.cywrk` workspace,
+When you're ready, open the `FluxEngine.cydsn/FluxEngine.cyprj` project,
 pick 'Program' from the menu, and the firmware should compile and be
 programmed onto your board.
 
@@ -139,11 +175,6 @@ the port and proceed normally.
 
 ## Building the client
 
-**Before you read this:** If you're on Windows, good news! You can download a
-*precompiled version of the FluxEngine client [from the GitHub releases
-*page](https://github.com/davidgiven/fluxengine/releases/latest). Simply unzip
-*it somewhere and run it from a `cmd` window (or other shell).
-
 The client software is where the intelligence, such as it is, is. It's pretty
 generic libusb stuff and should build and run on Windows, Linux and OSX as
 well, although on Windows it'll need MSYS2 and mingw32. You'll need to
@@ -151,7 +182,7 @@ install some support packages.
 
   - For Linux (this is Ubuntu, but this should apply to Debian too):
   `ninja-build`, `libusb-1.0-0-dev`, `libsqlite3-dev`.
-  - For OSX with Homebrew: `ninja`.
+  - For OSX with Homebrew: `ninja`, `libusb`, `pkg-config`, `sqlite`.
   - For Windows with MSYS2: `make`, `ninja`, `mingw-w64-i686-libusb`,
   `mingw-w64-i686-sqlite3`, `mingw-w64-i686-zlib`, `mingw-w64-i686-gcc`.
 

doc/disk-amiga.md

@@ -23,6 +23,17 @@ You should end up with an `amiga.adf` which is 901120 bytes long (for a
 normal DD disk) --- it ought to be a perfectly normal ADF file which you can
 use in an emulator.
 
+If you want the metadata as well, specify a 528 byte sector size for the
+output image:
+
+```
+fluxengine read amiga -o amiga.adf:b=528
+```
+
+You will end up with a 929280 byte long image which you probably _can't_ use
+in an emulator; each sector will contain the 512 bytes of user payload
+followed by the 16 bytes of metadata.
+
 Useful references
 -----------------
 

doc/disk-brother.md

@@ -129,8 +129,8 @@ reverse engineered it to find out.
 
 Standard Linux mtools will access the filesystem image and allow you to move
 files in and out. However, you'll need to change the media type bytes at
-offsets 0x015 and 0x100 from 0x58 to 0xf0 before mtools will touch it. Once
-done, this will work:
+offsets 0x015 and 0x100 from 0x58 to 0xf0 before mtools will touch it. The
+supplied `brother240tool` will do this. Once done, this will work:
 
 ```
 mdir -i brother.img

doc/disk-c64.md

@@ -23,7 +23,7 @@ computer](https://ilesj.wordpress.com/2014/05/14/1541-why-so-complicated/) of
 300 bytes per second (!). (The drive itself could transfer data reasonably
 quickly.)
 
-A standard 1541 disk has 35 tracks of 17 to 20 sectors, each 256 bytes long.
+A standard 1541 disk has 35 tracks of 17 to 21 sectors, each 256 bytes long.
 
 Reading discs
 -------------
@@ -34,15 +34,14 @@ Just do:
 fluxengine read c64
 ```
 
-You should end up with an `c64.img` which is 187136 bytes long (for a normal
-1541 disk).
+You should end up with an `c64.d64` file which is 174848 bytes long. You can
+load this straight into a Commodore 64 emulator such as
+[VICE](http://vice-emu.sourceforge.net/).
 
-**Big warning!** The image may not work in an emulator. Commodore 64 disk images are
+**Big warning!** Commodore 64 disk images are
 complicated due to the way the tracks are different sizes and the odd sector
-size. FluxEngine chooses to store them in a simple 256 x 20 x 35 layout,
-with holes where missing sectors should be. This was easiest. If anyone can
-suggest a better way, please [get in
-touch](https://github.com/davidgiven/fluxengine/issues/new).
+size, so you need the special D64 or LDBS output formats to represent them
+sensibly. Don't use IMG unless you know what you're doing.
 
 Useful references
 -----------------

doc/disk-macintosh.md

@@ -28,8 +28,16 @@ for example the Commodore 64 1541 drive, changed bitrate this way.
 But Macintosh disks used a constant bitrate and changed the speed that the
 disk spun instead to achieve the same effect...
 
-_Anyway_: FluxEngine will read them fine on a conventional drive. Because
-it's clever.
+_Anyway_: FluxEngine will read them fine on conventional drives.
+Because it's clever.
+
+**Big note.** Apparently --- and I'm still getting to the bottom of this ---
+some drives work and some don't. My drives produce about 90% good reads of
+known good disks. One rumour I've heard is that drives sometimes include
+filters which damage the signals at very particular intervals which Mac disks
+use, but frankly this seems unlikely; it could be a software issue at my end
+and I'm investigating. If you have any insight, please [get in
+touch](https://github.com/davidgiven/fluxengine/issues/new).
 
 Reading discs
 -------------
@@ -50,6 +58,10 @@ with holes where missing sectors should be. This was easiest. If anyone can
 suggest a better way, please [get in
 touch](https://github.com/davidgiven/fluxengine/issues/new).
 
+The 12 bytes of metadata _follow_ the 512 bytes of user payload in the sector
+image. If you don't want it, specify a geometry in the output file with a
+512-byte sectore size like `-o mac.img:c=80:h=1:s=12:b=512`.
+
 Useful references
 -----------------
 

doc/disk-mx.md

@@ -0,0 +1,65 @@
+Disk: DVK MX
+============
+
+The DVK (in Russian, ДВК, Диалоговый вычислительный комплекс or Dialogue
+Computing Complex) was a late 1970s Soviet personal computer, a cut-down
+version of the professional SM EVM (СМ ЭВМ, abbreviation of Система Малых ЭВМ
+--- literally System of Mini Computers), which _itself_ was an unlicensed
+clone of the PDP-11. The MX board was an early floppy drive controller board
+for it.
+
+<div style="text-align: center">
+<a href="http://www.leningrad.su/museum/show_big.php?n=1006"><img src="dvk3m.jpg" style="max-width: 60%" alt="A Durango F85, held precariously"></a>
+</div>
+
+The MX format is interesting in that it has to be read a track at a time. The
+format contains the usual ID prologue at the beginning of the track, then
+eleven data blocks and checksums, then the epilogue, then it stops. The
+actual encoding is normal FM. There were four different disk variants, in all
+combinations of single- and double-sided and 40- and 80-tracked; but every
+track contained eleven 256-byte sectors.
+
+The format varies subtly depending on whether you're using the 'new' driver
+or the 'old' driver. FluxEngine should read both.
+
+A track is:
+
+  * 8 x 0x0000 words (FM encoded as 01010101...)
+  * 1 x 0x00F3 --- start of track
+  * 1 x 0xnnnn --- track number
+  * 11 of:
+    * 128 words (256 bytes) of data
+    * 16 bit checksum
+  * **if 'new' format:**
+    * 3 x 0x83nn --- `n = (track_number<<1) + side_number`
+  * **if 'old' format:**
+    * 3 x 0x8301
+
+The checksum is just the unsigned integer sum of all the words in the sector.
+Words are all stored little-endian.
+
+Reading discs
+-------------
+
+```
+fluxengine read mx
+```
+
+You should end up with an `mx.img` which will vary in length depending on the format. The default is double-sided 80-track. For the other formats, use:
+
+  * single-sided 40-track: `-s :s=0:t=0-79x2`
+  * double-sided 40-track: `-s :s=0-1:t=0-79x2`
+  * single-sided 40-track: `-s :s=0:t=0-79`
+  * double-sided 40-track: `-s :s=0-1:t=0-79`
+
+
+Useful references
+-----------------
+
+  - [The Soviet Digital Electronics
+    Museum](http://www.leningrad.su/museum/main.php) (source of the image
+    above)
+
+  - [a random post on the HxC2001 support
+    forum](http://torlus.com/floppy/forum/viewtopic.php?t=1384) with lots of
+    information on the format

doc/faq.md

@@ -48,7 +48,7 @@ haven't had the chance to try it end-for-end. I really need a hard-sectored
 
 **Q.** Does it work with flippy disks?
 
-Uhhh... probably not.
+Uhhh... maybe?
 
 So the problem with flippy disks (5.25" single-sided disks which could be
 inserted upside down to read the second side) is the index hole. Trouble is,
@@ -79,16 +79,21 @@ the other. But a flippy disk has both sets of tracks in the same place,
 because they're both accessed using the side 0 head...
 
 The only real way round this is to modify a 5.25" drive. That's _seriously_
-not in FluxEngine's remit. Sorry.
+not in FluxEngine's remit, but I've had some [excellent documentation
+contributed](Index_sensor_mod_FDD_1.1.pdf) on how to do this. I've never done
+it myself; if you try this and it works/doesn't work, as always, [get in
+touch](https://github.com/davidgiven/fluxengine/issues/new).
 
-**Q.** Is this like KryoFlux / Catweasel / DiskFerret? Do you support KryoFlux
+**Q.** Is this like Supercard Pro / KryoFlux / Catweasel / DiskFerret? Do you
+*support KryoFlux
 stream files?
 
 **A.** It's very like all of these; the idea's old, and lots of people have
 tried it (you can get away with any sufficiently fast microcontroller and
 enough RAM). FluxEngine can read from KryoFlux stream files natively, and
-there's a tool which will let you convert at least one kind of Catweasel file
-to FluxEngine's native flux file format.
+there's a tool which will let you convert at least one kind of Catweasel
+files and Supercard Pro files to and from FluxEngine's native flux file
+format.
 
 **Q.** Can I use this to make exact copies of disks?
 

doc/technical.md

@@ -123,8 +123,12 @@ admittedly expensive.)
     sheet](http://www.bitsavers.org/pdf/mitsubishi/floppy/M4851/TJ2-G30211A_M4851_DSHH_48TPI_OEM_Manual_Nov83.pdf):
     the equivalent data sheet for a representative 5.25" drive.
 
+  - [The DRG Business Machines YD-174 manual](https://electrickery.hosting.philpem.me.uk/comp/divcomp/doc/YE_Data_YD-174_8inchFloppyDriveTechnicalManual.pdf):
+	the equivalent manual (data sheets hadn't been invented then) for a
+	representative 8" drive.
+
   - [KryoFlux stream file
     documentation](https://www.kryoflux.com/download/kryoflux_stream_protocol_rev1.1.pdf):
     the format of KryoFlux stream files (partially supported by FluxEngine)
 
-  
+  

doc/using.md

@@ -51,7 +51,7 @@ In order to do anything useful, you have to plug it in to a floppy disk drive (o
      rpm for a 3.5" disk, or 360 rpm for a 5.25" disk. If it doesn't, please
      [get in touch](https://github.com/davidgiven/fluxengine/issues/new).
 
-  7. Do `fluxengine testbulktransport` from the shell. It'll measure your USB
+  7. Do `fluxengine test bulktransport` from the shell. It'll measure your USB
      bandwidth. Ideally you should be getting above 900kB/s. FluxEngine needs
      about 850kB/s, so if you're getting less than this, try a different USB
      port.
@@ -112,6 +112,51 @@ sensible for the command you're using.
 **Important note:** FluxEngine _always_ uses zero-based units (even if the
 *disk format says otherwise).
 
+### Input and output specifiers
+
+These use a very similar syntax to the source and destination specifiers
+(because they're based on the same microformat library!) but are used for
+input and output _images_: i.e. nicely lined up arrays of sectors which you
+can actually do something with.
+
+Use `--input` (`-i`) or `--output` (`-o`) as appropriate to tell FluxEngine
+where you want to read from or write to. The actual format is autodetected
+based on the extension:
+
+  - `.img` or `.adf`: raw sector images in CHS order. Append
+    `:c=80:h=2:s=9:b=512` to set the geometry; that specifies 80 cylinders, 2
+    heads, 9 sectors, 512 bytes per sector. For output files (`--output`) the
+    geometry will be autodetected if left unspecified. For input files you
+    normally have to specify it.
+
+  - `.ldbs`: John Elliott's [LDBS disk image
+    format](http://www.seasip.info/Unix/LibDsk/ldbs.html), which is
+    consumable by the [libdsk](http://www.seasip.info/Unix/LibDsk/) suite of
+    tools. This allows things like variable numbers of sectors per track
+    (e.g. Macintosh or Commodore 64) and also provides information about
+    whether sectors were read correctly. You can use libdsk to convert this
+    to other formats, using a command like this:
+
+    ```
+    $ dsktrans out.ldbs -otype tele out.td0
+    ```
+
+    ...to convert to TeleDisk format. (Note you have to use dsktrans rather
+    than dskconv due to a minor bug in the geometry hadnling.)
+
+    FluxEngine's LDBS support is currently limited to write only, and
+    it doesn't store a lot of the more esoteric LDBS features like format
+    types, timings, and data rates.
+
+  - `.d64`: the venerable Commodore 64 disk image format as used by the 1540,
+    1541, etc. This is a special-purpose format due to the weird layout of
+    1540 disks and while you can use this for non-Commodore disks the result
+    will be gibberish. Use this to image Commodore 64 disks and load the
+    result into an emulator.
+
+    FluxEngine's D64 support is currently limited to write only. It will work
+    with up to 40 logical tracks.
+
 ### High density disks
 
 High density disks use a different magnetic medium to low and double density
@@ -168,18 +213,50 @@ directory.
   - `fluxengine seek`: moves the head. Mainly useful for finding out whether
   your drive can seek to track 82. (Mine can't.)
 
-  - `fluxengine testbulktransport`: measures your USB throughput. You need
+  - `fluxengine test bulktransport`: measures your USB throughput. You need
   about 600kB/s for FluxEngine to work. You don't need a disk in the drive
   for this one.
 
+  - `fluxengine test voltages`: measures your FDD bus signal voltages, which
+  is useful for testing for termination issues.
+
   - `fluxengine upgradefluxfile`: occasionally I need to upgrade the flux
   file format in a non-backwards-compatible way; this tool will upgrade flux
   files to the new format.
 
+  - `fluxengine convert`: converts flux files from various formats to various
+  other formats. You can use this to convert Catweasel flux files to
+  FluxEngine's native format, FluxEngine flux files to various other formats
+  useful for debugging (including VCD which can be loaded into
+  [sigrok](http://sigrok.org)), and bidirectional conversion to and from
+  Supercard Pro `.scp` format.
+
+  **Important SCP note:** import (`fluxengine convert scptoflux`) should be
+  fairly robust, but export (`fluxengine convert fluxtoscp`) should only be
+  done with great caution as FluxEngine files contain features which can't be
+  represented very well in `.scp` format and they're probably pretty dubious.
+  As ever, please [get in
+  touch](https://github.com/davidgiven/fluxengine/issues/new) with any reports.
+
 Commands which normally take `--source` or `--dest` get a sensible default if
 left unspecified. `fluxengine read ibm` on its own will read drive 0 and
 write an `ibm.img` file.
 
+## Visualisation
+
+When doing a read (either from a real disk or from a flux file) you can use
+`--write-svg=output.svg` to write out a graphical visualisation of where the
+sectors are on the disk. Here's a IBM PC 1232kB disk:
+
+![A disk visualisation](./visualiser.svg)
+
+Blue represents data, light blue a header, and red is a bad sector. Side zero
+is on the left and side one is on the right.
+
+The visualiser is extremely primitive and you have to explicitly tell it how
+big your disk is, in milliseconds. The default is 200ms (for a normal 3.5"
+disk). For a 5.25" disk, use `--visualiser-period=166`.
+
 ## Extra programs
 
 Supplied with FluxEngine, but not part of FluxEngine, are some little tools I
@@ -187,25 +264,24 @@ wrote to do useful things. These are built alongside FluxEngine.
 
   - `brother120tool`: extracts files from a 120kB Brother filesystem image.
 
-  - `cwftoflux`: converts (one flavour of) CatWeasel flux file into a
-    FluxEngine flux file.
-
 ## The recommended workflow
 
-So you've just received, say, a huge pile of old Brother word processor disks containing valuable historical data, and you want to read them.
+So you've just received, say, a huge pile of old Brother word processor disks
+containing valuable historical data, and you want to read them.
 
 Typically I do this:
 
 ```
-$ fluxengine read brother -s :d=0 -o brother.img --write-flux=brother.flux
+$ fluxengine read brother -s :d=0 -o brother.img --write-flux=brother.flux --write-svg=brother.svg
 ```
 
 This will read the disk in drive 0 and write out a filesystem image. It'll
-also copy the flux to brother.flux. If I then need to tweak the settings, I
-can rerun the decode without having to physically touch the disk like this:
+also copy the flux to brother.flux and write out an SVG visualisation. If I
+then need to tweak the settings, I can rerun the decode without having to
+physically touch the disk like this:
 
 ```
-$ fluxengine read brother -s brother.flux -o brother.img
+$ fluxengine read brother -s brother.flux -o brother.img --write-svg=brother.svg
 ```
 
 Apart from being drastically faster, this avoids touching the (potentially

lib/brother/encoder.cc

@@ -1,92 +0,0 @@
-#include "globals.h"
-#include "record.h"
-#include "decoders/decoders.h"
-#include "brother.h"
-#include "crc.h"
-
-static int encode_header_gcr(uint16_t word)
-{
-	switch (word)
-	{
-		#define GCR_ENTRY(gcr, data) \
-			case data: return gcr;
-		#include "header_gcr.h"
-		#undef GCR_ENTRY
-	}                       
-	return -1;             
-};
-
-static int encode_data_gcr(uint8_t data)
-{
-	switch (data)
-	{
-		#define GCR_ENTRY(gcr, data) \
-			case data: return gcr;
-		#include "data_gcr.h"
-		#undef GCR_ENTRY
-	}                       
-	return -1;             
-};
-
-static void write_bits(std::vector<bool>& bits, unsigned& cursor, uint32_t data, int width)
-{
-	cursor += width;
-	for (int i=0; i<width; i++)
-	{
-		unsigned pos = cursor - i - 1;
-		if (pos < bits.size())
-			bits[pos] = data & 1;
-		data >>= 1;
-	}
-}
-
-void writeBrotherSectorHeader(std::vector<bool>& bits, unsigned& cursor,
-		int track, int sector)
-{
-	write_bits(bits, cursor, 0xffffffff, 31);
-	write_bits(bits, cursor, BROTHER_SECTOR_RECORD, 32);
-	write_bits(bits, cursor, encode_header_gcr(track), 16);
-	write_bits(bits, cursor, encode_header_gcr(sector), 16);
-	write_bits(bits, cursor, encode_header_gcr(0x2f), 16);
-}
-
-void writeBrotherSectorData(std::vector<bool>& bits, unsigned& cursor, const Bytes& data)
-{
-	write_bits(bits, cursor, 0xffffffff, 32);
-	write_bits(bits, cursor, BROTHER_DATA_RECORD, 32);
-
-	uint16_t fifo = 0;
-	int width = 0;
-
-	if (data.size() != BROTHER_DATA_RECORD_PAYLOAD)
-		Error() << "unsupported sector size";
-
-	auto write_byte = [&](uint8_t byte)
-	{
-		fifo |= (byte << (8 - width));
-		width += 8;
-
-		while (width >= 5)
-		{
-			uint8_t quintet = fifo >> 11;
-			fifo <<= 5;
-			width -= 5;
-
-			write_bits(bits, cursor, encode_data_gcr(quintet), 8);
-		}
-	};
-
-	for (uint8_t byte : data)
-		write_byte(byte);
-
-	uint32_t realCrc = crcbrother(data);
-	write_byte(realCrc>>16);
-	write_byte(realCrc>>8);
-	write_byte(realCrc);
-	write_byte(0x58); /* magic */
-    write_byte(0xd4);
-    while (width != 0)
-        write_byte(0);
-}
-
-

lib/bytes.cc

@@ -2,6 +2,7 @@
 #include "bytes.h"
 #include "fmt/format.h"
 #include "common/crunch.h"
+#include <fstream>
 #include <zlib.h>
 
 static std::shared_ptr<std::vector<uint8_t>> createVector(unsigned size)
@@ -280,6 +281,16 @@ Bytes Bytes::uncrunch() const
     return output;
 }
 
+void Bytes::writeToFile(const std::string& filename) const
+{
+    std::ofstream f(filename, std::ios::out | std::ios::binary);
+    if (!f.is_open())
+        Error() << fmt::format("cannot open output file '{}'", filename);
+
+    f.write((const char*) cbegin(), size());
+    f.close();
+}
+
 ByteReader Bytes::reader() const
 {
     return ByteReader(*this);

lib/bytes.h

@@ -56,6 +56,8 @@ public:
     ByteReader reader() const;
     ByteWriter writer();
 
+    void writeToFile(const std::string& filename) const;
+
 private:
     std::shared_ptr<std::vector<uint8_t>> _data;
     unsigned _low;

lib/dataspec.cc

@@ -5,6 +5,11 @@
 #include <regex>
 #include <sstream>
 
+MissingModifierException::MissingModifierException(const std::string& mod):
+    mod(mod),
+    std::runtime_error(fmt::format("missing mandatory modifier '{}'", mod))
+{}
+
 std::vector<std::string> DataSpec::split(
         const std::string& s, const std::string& delimiter)
 {
@@ -74,31 +79,108 @@ void DataSpec::set(const std::string& spec)
     filename = words[0];
     if (words.size() > 1)
     {
-        locations.clear();
-
         for (size_t i = 1; i < words.size(); i++)
         {
             auto mod = parseMod(words[i]);
-            if ((mod.name != "t") && (mod.name != "s") && (mod.name != "d"))
-                Error() << fmt::format("unknown data modifier '{}'", mod.name);
             modifiers[mod.name] = mod;
         }
+    }
+}
 
-        const auto& drives = modifiers["d"].data;
+const DataSpec::Modifier& DataSpec::at(const std::string& mod) const
+{
+    try
+    {
+        return modifiers.at(mod);
+    }
+    catch (const std::out_of_range& e)
+    {
+        throw MissingModifierException(mod);
+    }
+}
+
+bool DataSpec::has(const std::string& mod) const
+{
+    return modifiers.find(mod) != modifiers.end();
+}
+
+FluxSpec::FluxSpec(const DataSpec& spec)
+{
+    try 
+    {
+        filename = spec.filename;
+
+        locations.clear();
+
+        const auto& drives = spec.at("d").data;
         if (drives.size() != 1)
             Error() << "you must specify exactly one drive";
         drive = *drives.begin();
 
-        const auto& tracks = modifiers["t"].data;
-        const auto& sides = modifiers["s"].data;
+        const auto& tracks = spec.at("t").data;
+        const auto& sides = spec.at("s").data;
         for (auto track : tracks)
         {
             for (auto side : sides)
                 locations.push_back({ drive, track, side });
         }
+
+        for (const auto& e : spec.modifiers)
+        {
+            const auto name = e.second.name;
+            if ((name != "t") && (name != "s") && (name != "d"))
+                Error() << fmt::format("unknown fluxspec modifier '{}'", name);
+        }
+    }
+    catch (const MissingModifierException& e)
+    {
+        Error() << e.what() << " in fluxspec '" << spec << "'";
     }
 }
 
+ImageSpec::ImageSpec(const DataSpec& spec)
+{
+    try
+    {
+        filename = spec.filename;
+
+        if (!spec.has("c") && !spec.has("h") && !spec.has("s") && !spec.has("b"))
+        {
+            cylinders = heads = sectors = bytes = 0;
+            initialised = false;
+        }
+        else
+        {
+            cylinders = spec.at("c").only();
+            heads = spec.at("h").only();
+            sectors = spec.at("s").only();
+            bytes = spec.at("b").only();
+            initialised = true;
+        }
+    }
+    catch (const MissingModifierException& e)
+    {
+        Error() << e.what() << " in imagespec '" << spec << "'";
+    }
+
+    for (const auto& e : spec.modifiers)
+    {
+        const auto name = e.second.name;
+        if ((name != "c") && (name != "h") && (name != "s") && (name != "b"))
+            Error() << fmt::format("unknown fluxspec modifier '{}'", name);
+    }
+}
+
+ImageSpec::ImageSpec(const std::string filename,
+        unsigned cylinders, unsigned heads, unsigned sectors, unsigned bytes):
+    filename(filename),
+    cylinders(cylinders),
+    heads(heads),
+    sectors(sectors),
+    bytes(bytes),
+    initialised(true)
+{}
+
 DataSpec::operator std::string(void) const
 {
     std::stringstream ss;

lib/dataspec.h

@@ -1,8 +1,57 @@
 #ifndef DATASPEC_H
 #define DATASPEC_H
 
+class MissingModifierException : public std::runtime_error
+{
+public:
+    MissingModifierException(const std::string& mod);
+    const std::string mod;
+};
+
 class DataSpec
 {
+public:
+    struct Modifier
+    {
+        std::string name;
+        std::set<unsigned> data;
+        std::string source;
+
+        bool operator == (const Modifier& other) const
+        { return (name == other.name) && (data == other.data); }
+
+        bool operator != (const Modifier& other) const
+        { return (name != other.name) || (data != other.data); }
+
+        unsigned only() const
+        {
+            if (data.size() != 1)
+                Error() << "modifier " << name << " can only have one value";
+            return *(data.begin());
+        }
+    };
+
+public:
+    static std::vector<std::string> split(
+        const std::string& s, const std::string& delimiter);
+    static Modifier parseMod(const std::string& spec);
+
+public:
+    DataSpec(const std::string& spec)
+    { set(spec); }
+
+    void set(const std::string& spec);
+    operator std::string () const;
+
+    const Modifier& at(const std::string& mod) const;
+    bool has(const std::string& mod) const;
+
+    std::string filename;
+    std::map<std::string, Modifier> modifiers;
+};
+
+class FluxSpec
+{
 public:
     struct Location
     {
@@ -17,36 +66,29 @@ public:
         { return (drive != other.drive) || (track != other.track) || (side != other.side); }
     };
 
-    struct Modifier
-    {
-        std::string name;
-        std::set<unsigned> data;
-        std::string source;
-
-        bool operator == (const Modifier& other) const
-        { return (name == other.name) && (data == other.data); }
-
-        bool operator != (const Modifier& other) const
-        { return (name != other.name) || (data != other.data); }
-    };
+public:
+    FluxSpec(const DataSpec& dataspec);
 
 public:
-    static std::vector<std::string> split(
-        const std::string& s, const std::string& delimiter);
-    static Modifier parseMod(const std::string& spec);
-
-public:
-    DataSpec(const std::string& spec)
-    { set(spec); }
-
-    void set(const std::string& spec);
-    operator std::string () const;
-
     std::string filename;
-    std::map<std::string, Modifier> modifiers;
     std::vector<Location> locations;
     unsigned drive;
-    unsigned revolutions;
+};
+
+class ImageSpec
+{
+public:
+    ImageSpec(const DataSpec& dataspec);
+    ImageSpec(const std::string filename,
+        unsigned cylinders, unsigned heads, unsigned sectors, unsigned bytes);
+
+public:
+    std::string filename;
+    unsigned cylinders;
+    unsigned heads;
+    unsigned sectors;
+    unsigned bytes;
+    bool initialised : 1;
 };
 
 static inline std::ostream& operator << (std::ostream& os, const DataSpec& dataSpec)

lib/decoders/decoders.cc

@@ -43,19 +43,25 @@ void AbstractDecoder::decodeToSectors(Track& track)
 
         recordStart = fmr.tell();
         decodeSectorRecord();
-        pushRecord(recordStart, fmr.tell());
+        Fluxmap::Position recordEnd = fmr.tell();
+        pushRecord(recordStart, recordEnd);
         if (sector.status == Sector::DATA_MISSING)
         {
             /* The data is in a separate record. */
 
+            sector.headerStartTime = recordStart.ns();
+            sector.headerEndTime = recordEnd.ns();
             r = advanceToNextRecord();
             if (r == DATA_RECORD)
             {
                 recordStart = fmr.tell();
                 decodeDataRecord();
-                pushRecord(recordStart, fmr.tell());
+                recordEnd = fmr.tell();
+                pushRecord(recordStart, recordEnd);
             }
         }
+        sector.dataStartTime = recordStart.ns();
+        sector.dataEndTime = recordEnd.ns();
 
         if (sector.status != Sector::MISSING)
             track.sectors.push_back(sector);

lib/encoders/encoders.h

@@ -0,0 +1,18 @@
+#ifndef ENCODERS_H
+#define ENCODERS_H
+
+class Fluxmap;
+class SectorSet;
+
+class AbstractEncoder
+{
+public:
+    virtual ~AbstractEncoder() {}
+
+public:
+    virtual std::unique_ptr<Fluxmap> encode(
+        int physicalTrack, int physicalSide, const SectorSet& allSectors) = 0;
+};
+
+#endif
+

lib/flags.cc

@@ -29,7 +29,7 @@ void FlagGroup::addFlag(Flag* flag)
     _flags.push_back(flag);
 }
 
-void FlagGroup::parseFlags(int argc, const char* argv[])
+std::vector<std::string> FlagGroup::parseFlagsWithFilenames(int argc, const char* argv[])
 {
     if (_initialised)
         throw std::runtime_error("called parseFlags() twice");
@@ -66,6 +66,7 @@ void FlagGroup::parseFlags(int argc, const char* argv[])
 
     /* Now actually parse them. */
 
+    std::vector<std::string> filenames;
     int index = 1;
     while (index < argc)
     {
@@ -76,52 +77,73 @@ void FlagGroup::parseFlags(int argc, const char* argv[])
         std::string value;
         bool usesthat = false;
 
-        if ((thisarg.size() == 0) || (thisarg[0] != '-'))
-            Error() << "non-option parameter " << thisarg << " seen (try --help)";
-        if ((thisarg.size() > 1) && (thisarg[1] == '-'))
+        if (thisarg.size() == 0)
         {
-            /* Long option. */
-
-            auto equals = thisarg.rfind('=');
-            if (equals != std::string::npos)
-            {
-                key = thisarg.substr(0, equals);
-                value = thisarg.substr(equals+1);
-            }
-            else
-            {
-                key = thisarg;
-                value = thatarg;
-                usesthat = true;
-            }
+            /* Ignore this argument. */
+        }
+        else if (thisarg[0] != '-')
+        {
+            /* This is a filename. */
+            filenames.push_back(thisarg);
         }
         else
         {
-            /* Short option. */
+            /* This is a flag. */
 
-            if (thisarg.size() > 2)
+            if ((thisarg.size() > 1) && (thisarg[1] == '-'))
             {
-                key = thisarg.substr(0, 2);
-                value = thisarg.substr(2);
+                /* Long option. */
+
+                auto equals = thisarg.rfind('=');
+                if (equals != std::string::npos)
+                {
+                    key = thisarg.substr(0, equals);
+                    value = thisarg.substr(equals+1);
+                }
+                else
+                {
+                    key = thisarg;
+                    value = thatarg;
+                    usesthat = true;
+                }
             }
             else
             {
-                key = thisarg;
-                value = thatarg;
-                usesthat = true;
+                /* Short option. */
+
+                if (thisarg.size() > 2)
+                {
+                    key = thisarg.substr(0, 2);
+                    value = thisarg.substr(2);
+                }
+                else
+                {
+                    key = thisarg;
+                    value = thatarg;
+                    usesthat = true;
+                }
             }
+
+            auto flag = flags_by_name.find(key);
+            if (flag == flags_by_name.end())
+                Error() << "unknown flag '" << key << "'; try --help";
+
+            flag->second->set(value);
+            if (usesthat && flag->second->hasArgument())
+                index++;
         }
 
-        auto flag = flags_by_name.find(key);
-        if (flag == flags_by_name.end())
-            Error() << "unknown flag '" << key << "'; try --help";
-
-        flag->second->set(value);
-
         index++;
-        if (usesthat && flag->second->hasArgument())
-            index++;
     }
+
+    return filenames;
+}
+
+void FlagGroup::parseFlags(int argc, const char* argv[])
+{
+    auto filenames = parseFlagsWithFilenames(argc, argv);
+    if (!filenames.empty())
+        Error() << "non-option parameter " << *filenames.begin() << " seen (try --help)";
 }
 
 void FlagGroup::checkInitialised() const

lib/flags.h

@@ -14,6 +14,7 @@ public:
 
 public:
     void parseFlags(int argc, const char* argv[]);
+    std::vector<std::string> parseFlagsWithFilenames(int argc, const char* argv[]);
     void addFlag(Flag* flag);
     void checkInitialised() const;
 

lib/fluxmap.h

@@ -21,6 +21,7 @@ public:
 
 public:
     nanoseconds_t duration() const { return _duration; }
+    unsigned ticks() const { return _ticks; }
     size_t bytes() const { return _bytes.size(); }
     const Bytes& rawBytes() const { return _bytes; }
 

lib/fluxsink/fluxsink.cc

@@ -10,7 +10,7 @@ static bool ends_with(const std::string& value, const std::string& ending)
     return std::equal(ending.rbegin(), ending.rend(), value.rbegin());
 }
 
-std::unique_ptr<FluxSink> FluxSink::create(const DataSpec& spec)
+std::unique_ptr<FluxSink> FluxSink::create(const FluxSpec& spec)
 {
     const auto& filename = spec.filename;
 

lib/fluxsink/fluxsink.h

@@ -2,7 +2,7 @@
 #define FLUXSINK_H
 
 class Fluxmap;
-class DataSpec;
+class FluxSpec;
 
 class FluxSink
 {
@@ -14,7 +14,7 @@ private:
     static std::unique_ptr<FluxSink> createHardwareFluxSink(unsigned drive);
 
 public:
-    static std::unique_ptr<FluxSink> create(const DataSpec& spec);
+    static std::unique_ptr<FluxSink> create(const FluxSpec& spec);
 
 public:
     virtual void writeFlux(int track, int side, Fluxmap& fluxmap) = 0;

lib/fluxsource/fluxsource.cc

@@ -10,7 +10,7 @@ static bool ends_with(const std::string& value, const std::string& ending)
     return std::equal(ending.rbegin(), ending.rend(), value.rbegin());
 }
 
-std::unique_ptr<FluxSource> FluxSource::create(const DataSpec& spec)
+std::unique_ptr<FluxSource> FluxSource::create(const FluxSpec& spec)
 {
     const auto& filename = spec.filename;
 

lib/fluxsource/fluxsource.h

@@ -6,7 +6,7 @@
 extern FlagGroup hardwareFluxSourceFlags;
 
 class Fluxmap;
-class DataSpec;
+class FluxSpec;
 
 class FluxSource
 {
@@ -19,7 +19,7 @@ private:
     static std::unique_ptr<FluxSource> createStreamFluxSource(const std::string& path);
 
 public:
-    static std::unique_ptr<FluxSource> create(const DataSpec& spec);
+    static std::unique_ptr<FluxSource> create(const FluxSpec& spec);
 
 public:
     virtual std::unique_ptr<Fluxmap> readFlux(int track, int side) = 0;

lib/fluxsource/streamfluxsource.cc

@@ -24,7 +24,7 @@ public:
     void recalibrate() {}
 
 private:
-    const std::string& _path;
+    const std::string _path;
 };
 
 std::unique_ptr<FluxSource> FluxSource::createStreamFluxSource(const std::string& path)

lib/globals.h

@@ -22,7 +22,7 @@ extern void hexdumpForSrp16(std::ostream& stream, const Bytes& bytes);
 class Error
 {
 public:
-    ~Error()
+    [[ noreturn ]] ~Error()
     {
         std::cerr << "Error: " << _stream.str() << std::endl;
         exit(1);

lib/image.cc

@@ -1,150 +1,25 @@
 #include "globals.h"
 #include "image.h"
+#include "flags.h"
+#include "dataspec.h"
 #include "sector.h"
 #include "sectorset.h"
+#include "imagereader/imagereader.h"
+#include "imagewriter/imagewriter.h"
 #include "fmt/format.h"
 #include <algorithm>
 #include <iostream>
 #include <fstream>
 
-Geometry guessGeometry(const SectorSet& sectors)
+SectorSet readSectorsFromFile(const ImageSpec& spec)
 {
-	Geometry g;
-	sectors.calculateSize(g.tracks, g.heads, g.sectors, g.sectorSize);
-	return g;
+	return ImageReader::create(spec)->readImage();
 }
 
-void readSectorsFromFile(SectorSet& sectors, const Geometry& geometry,
-		const std::string& filename)
+void writeSectorsToFile(const SectorSet& sectors, const ImageSpec& spec)
 {
-    std::ifstream inputFile(filename, std::ios::in | std::ios::binary);
-    if (!inputFile.is_open())
-		Error() << "cannot open input file";
-
-    size_t headSize = geometry.sectors * geometry.sectorSize;
-    size_t trackSize = headSize * geometry.heads;
-
-    std::cout << fmt::format("{} tracks, {} heads, {} sectors, {} bytes per sector, {} kB total",
-					geometry.tracks, geometry.heads,
-					geometry.sectors, geometry.sectorSize,
-					geometry.tracks * trackSize / 1024)
-			  << std::endl;
-
-	for (int track = 0; track < geometry.tracks; track++)
-	{
-		for (int head = 0; head < geometry.heads; head++)
-		{
-			for (int sectorId = 0; sectorId < geometry.sectors; sectorId++)
-			{
-				inputFile.seekg(track*trackSize + head*headSize + sectorId*geometry.sectorSize, std::ios::beg);
-
-				Bytes data(geometry.sectorSize);
-				inputFile.read((char*) data.begin(), geometry.sectorSize);
-
-				std::unique_ptr<Sector>& sector = sectors.get(track, head, sectorId);
-				sector.reset(new Sector);
-				sector->status = Sector::OK;
-				sector->logicalTrack = sector->physicalTrack = track;
-				sector->logicalSide = sector->physicalSide = head;
-				sector->logicalSector = sectorId;
-				sector->data = data;
-			}
-		}
-	}
-}
-
-void writeSectorsToFile(const SectorSet& sectors, const Geometry& geometry,
-		const std::string& filename)
-{
-	/* Emit the map. */
-
-	int badSectors = 0;
-	int missingSectors = 0;
-	int totalSectors = 0;
-	std::cout << "H.SS Tracks --->" << std::endl;
-	for (int head = 0; head < geometry.heads; head++)
-	{
-		for (int sectorId = 0; sectorId < geometry.sectors; sectorId++)
-		{
-			std::cout << fmt::format("{}.{:2} ", head, sectorId);
-			for (int track = 0; track < geometry.tracks; track++)
-			{
-				Sector* sector = sectors.get(track, head, sectorId);
-				if (!sector)
-				{
-					std::cout << 'X';
-					missingSectors++;
-				}
-				else
-				{
-					switch (sector->status)
-					{
-						case Sector::OK:
-                            std::cout << '.';
-                            break;
-
-                        case Sector::BAD_CHECKSUM:
-                            std::cout << 'B';
-                            badSectors++;
-                            break;
-
-                        case Sector::CONFLICT:
-                            std::cout << 'C';
-                            badSectors++;
-                            break;
-
-                        default:
-                            std::cout << '?';
-                            break;
-                    }
-				}
-				totalSectors++;
-			}
-			std::cout << std::endl;
-		}
-	}
-	int goodSectors = totalSectors - missingSectors - badSectors;
-	if (totalSectors == 0)
-		std::cout << "No sectors in output; skipping analysis" << std::endl;
-	else
-	{
-		std::cout << "Good sectors: " << goodSectors << "/" << totalSectors
-				  << " (" << (100*goodSectors/totalSectors) << "%)"
-				  << std::endl;
-		std::cout << "Missing sectors: " << missingSectors << "/" << totalSectors
-				  << " (" << (100*missingSectors/totalSectors) << "%)"
-				  << std::endl;
-		std::cout << "Bad sectors: " << badSectors << "/" << totalSectors
-				  << " (" << (100*badSectors/totalSectors) << "%)"
-				  << std::endl;
-    }
-
-    size_t headSize = geometry.sectors * geometry.sectorSize;
-    size_t trackSize = headSize * geometry.heads;
-
-    std::cout << fmt::format("{} tracks, {} heads, {} sectors, {} bytes per sector, {} kB total",
-					geometry.tracks, geometry.heads,
-					geometry.sectors, geometry.sectorSize,
-					geometry.tracks * trackSize / 1024)
-			  << std::endl;
-
-    std::ofstream outputFile(filename, std::ios::out | std::ios::binary);
-    if (!outputFile.is_open())
-		Error() << "cannot open output file";
-
-	for (int track = 0; track < geometry.tracks; track++)
-	{
-		for (int head = 0; head < geometry.heads; head++)
-		{
-			for (int sectorId = 0; sectorId < geometry.sectors; sectorId++)
-			{
-				auto sector = sectors.get(track, head, sectorId);
-				if (sector)
-				{
-					outputFile.seekp(sector->logicalTrack*trackSize + sector->logicalSide*headSize + sector->logicalSector*geometry.sectorSize, std::ios::beg);
-					outputFile.write((const char*) sector->data.cbegin(), sector->data.size());
-				}
-			}
-		}
-	}
+	std::unique_ptr<ImageWriter> writer(ImageWriter::create(sectors, spec));
+	writer->adjustGeometry();
+	writer->printMap();
+	writer->writeImage();
 }

lib/image.h

@@ -2,26 +2,13 @@
 #define IMAGE_H
 
 class SectorSet;
+class ImageSpec;
 
-class Geometry
-{
-public:
-	int tracks;
-	int heads;
-	int sectors;
-	int sectorSize;
-};
-
-extern Geometry guessGeometry(const SectorSet& sectors);
-
-extern void readSectorsFromFile(
-	SectorSet& sectors,
-	const Geometry& geometry,
-	const std::string& filename);
+extern SectorSet readSectorsFromFile(
+	const ImageSpec& filename);
 
 extern void writeSectorsToFile(
 	const SectorSet& sectors,
-	const Geometry& geometry,
-	const std::string& filename);
+	const ImageSpec& filename);
 
 #endif

lib/imagereader/imagereader.cc

@@ -0,0 +1,52 @@
+#include "globals.h"
+#include "image.h"
+#include "flags.h"
+#include "dataspec.h"
+#include "sector.h"
+#include "sectorset.h"
+#include "imagereader/imagereader.h"
+#include "fmt/format.h"
+
+std::map<std::string, ImageReader::Constructor> ImageReader::formats =
+{
+	{".adf", ImageReader::createImgImageReader},
+	{".d81", ImageReader::createImgImageReader},
+	{".img", ImageReader::createImgImageReader},
+};
+
+static bool ends_with(const std::string& value, const std::string& ending)
+{
+    if (ending.size() > value.size())
+        return false;
+    return std::equal(ending.rbegin(), ending.rend(), value.rbegin());
+}
+
+ImageReader::Constructor ImageReader::findConstructor(const ImageSpec& spec)
+{
+    const auto& filename = spec.filename;
+
+	for (const auto& e : formats)
+	{
+		if (ends_with(filename, e.first))
+			return e.second;
+	}
+
+	return NULL;
+}
+
+std::unique_ptr<ImageReader> ImageReader::create(const ImageSpec& spec)
+{
+    verifyImageSpec(spec);
+    return findConstructor(spec)(spec);
+}
+
+void ImageReader::verifyImageSpec(const ImageSpec& spec)
+{
+    if (!findConstructor(spec))
+        Error() << "unrecognised image filename extension";
+}
+
+ImageReader::ImageReader(const ImageSpec& spec):
+    spec(spec)
+{}
+

lib/imagereader/imagereader.h

@@ -0,0 +1,38 @@
+#ifndef IMAGEREADER_H
+#define IMAGEREADER_H
+
+class SectorSet;
+class ImageSpec;
+
+class ImageReader
+{
+public:
+	ImageReader(const ImageSpec& spec);
+	virtual ~ImageReader() {};
+
+public:
+    static std::unique_ptr<ImageReader> create(const ImageSpec& spec);
+	static void verifyImageSpec(const ImageSpec& spec);
+
+private:
+	typedef 
+		std::function<
+			std::unique_ptr<ImageReader>(const ImageSpec& spec)
+		>
+		Constructor;
+
+	static std::map<std::string, Constructor> formats;
+
+    static std::unique_ptr<ImageReader> createImgImageReader(const ImageSpec& spec);
+
+	static Constructor findConstructor(const ImageSpec& spec);
+
+public:
+	virtual SectorSet readImage() = 0;
+
+protected:
+	ImageSpec spec;
+};
+
+#endif
+

lib/imagereader/imgimagereader.cc

@@ -0,0 +1,66 @@
+#include "globals.h"
+#include "image.h"
+#include "flags.h"
+#include "dataspec.h"
+#include "sector.h"
+#include "sectorset.h"
+#include "imagereader/imagereader.h"
+#include "fmt/format.h"
+#include <algorithm>
+#include <iostream>
+#include <fstream>
+
+class ImgImageReader : public ImageReader
+{
+public:
+	ImgImageReader(const ImageSpec& spec):
+		ImageReader(spec)
+	{}
+
+	SectorSet readImage()
+	{
+        std::ifstream inputFile(spec.filename, std::ios::in | std::ios::binary);
+        if (!inputFile.is_open())
+            Error() << "cannot open input file";
+
+        size_t headSize = spec.sectors * spec.bytes;
+        size_t trackSize = headSize * spec.heads;
+
+        std::cout << fmt::format("reading {} tracks, {} heads, {} sectors, {} bytes per sector, {} kB total",
+                        spec.cylinders, spec.heads,
+                        spec.sectors, spec.bytes,
+                        spec.cylinders * trackSize / 1024)
+                << std::endl;
+
+        SectorSet sectors;
+        for (int track = 0; track < spec.cylinders; track++)
+        {
+            for (int head = 0; head < spec.heads; head++)
+            {
+                for (int sectorId = 0; sectorId < spec.sectors; sectorId++)
+                {
+                    inputFile.seekg(track*trackSize + head*headSize + sectorId*spec.bytes, std::ios::beg);
+
+                    Bytes data(spec.bytes);
+                    inputFile.read((char*) data.begin(), spec.bytes);
+
+                    std::unique_ptr<Sector>& sector = sectors.get(track, head, sectorId);
+                    sector.reset(new Sector);
+                    sector->status = Sector::OK;
+                    sector->logicalTrack = sector->physicalTrack = track;
+                    sector->logicalSide = sector->physicalSide = head;
+                    sector->logicalSector = sectorId;
+                    sector->data = data;
+                }
+            }
+        }
+        return sectors;
+	}
+};
+
+std::unique_ptr<ImageReader> ImageReader::createImgImageReader(
+	const ImageSpec& spec)
+{
+    return std::unique_ptr<ImageReader>(new ImgImageReader(spec));
+}
+

lib/imagewriter/d64imagewriter.cc

@@ -0,0 +1,64 @@
+#include "globals.h"
+#include "image.h"
+#include "flags.h"
+#include "dataspec.h"
+#include "sector.h"
+#include "sectorset.h"
+#include "imagewriter/imagewriter.h"
+#include "fmt/format.h"
+#include "ldbs.h"
+#include <algorithm>
+#include <iostream>
+#include <fstream>
+
+static int sectors_per_track(int track)
+{
+    if (track < 17)
+        return 21;
+    if (track < 24)
+        return 19;
+    if (track < 30)
+        return 18;
+    return 17;
+}
+
+class D64ImageWriter : public ImageWriter
+{
+public:
+	D64ImageWriter(const SectorSet& sectors, const ImageSpec& spec):
+		ImageWriter(sectors, spec)
+	{}
+
+	void writeImage()
+	{
+		std::cout << "writing D64 triangular image\n";
+
+		std::ofstream outputFile(spec.filename, std::ios::out | std::ios::binary);
+		if (!outputFile.is_open())
+			Error() << "cannot open output file";
+
+        uint32_t offset = 0;
+		for (int track = 0; track < 40; track++)
+		{
+            int sectorCount = sectors_per_track(track);
+            for (int sectorId = 0; sectorId < sectorCount; sectorId++)
+            {
+                const auto& sector = sectors.get(track, 0, sectorId);
+                if (sector)
+                {
+                    outputFile.seekp(offset);
+                    outputFile.write((const char*) sector->data.cbegin(), 256);
+                }
+
+                offset += 256;
+            }
+		}
+    }
+};
+
+std::unique_ptr<ImageWriter> ImageWriter::createD64ImageWriter(
+	const SectorSet& sectors, const ImageSpec& spec)
+{
+    return std::unique_ptr<ImageWriter>(new D64ImageWriter(sectors, spec));
+}
+

lib/imagewriter/imagewriter.cc

@@ -0,0 +1,128 @@
+#include "globals.h"
+#include "image.h"
+#include "flags.h"
+#include "dataspec.h"
+#include "sector.h"
+#include "sectorset.h"
+#include "imagewriter/imagewriter.h"
+#include "fmt/format.h"
+
+std::map<std::string, ImageWriter::Constructor> ImageWriter::formats =
+{
+	{".adf", ImageWriter::createImgImageWriter},
+	{".d64", ImageWriter::createD64ImageWriter},
+	{".d81", ImageWriter::createImgImageWriter},
+	{".img", ImageWriter::createImgImageWriter},
+	{".ldbs", ImageWriter::createLDBSImageWriter},
+};
+
+static bool ends_with(const std::string& value, const std::string& ending)
+{
+    if (ending.size() > value.size())
+        return false;
+    return std::equal(ending.rbegin(), ending.rend(), value.rbegin());
+}
+
+ImageWriter::Constructor ImageWriter::findConstructor(const ImageSpec& spec)
+{
+    const auto& filename = spec.filename;
+
+	for (const auto& e : formats)
+	{
+		if (ends_with(filename, e.first))
+			return e.second;
+	}
+
+	return NULL;
+}
+
+std::unique_ptr<ImageWriter> ImageWriter::create(const SectorSet& sectors, const ImageSpec& spec)
+{
+	verifyImageSpec(spec);
+	return findConstructor(spec)(sectors, spec);
+}
+
+void ImageWriter::verifyImageSpec(const ImageSpec& spec)
+{
+	if (!findConstructor(spec))
+		Error() << "unrecognised image filename extension";
+}
+
+ImageWriter::ImageWriter(const SectorSet& sectors, const ImageSpec& spec):
+    sectors(sectors),
+    spec(spec)
+{}
+
+void ImageWriter::adjustGeometry()
+{
+	if (!spec.initialised)
+	{
+		sectors.calculateSize(spec.cylinders, spec.heads, spec.sectors, spec.bytes);
+        spec.initialised = true;
+		std::cout << "Autodetecting output geometry\n";
+	}
+}
+
+void ImageWriter::printMap()
+{
+	int badSectors = 0;
+	int missingSectors = 0;
+	int totalSectors = 0;
+	std::cout << "H.SS Tracks --->" << std::endl;
+	for (int head = 0; head < spec.heads; head++)
+	{
+		for (int sectorId = 0; sectorId < spec.sectors; sectorId++)
+		{
+			std::cout << fmt::format("{}.{:2} ", head, sectorId);
+			for (int track = 0; track < spec.cylinders; track++)
+			{
+				const auto& sector = sectors.get(track, head, sectorId);
+				if (!sector)
+				{
+					std::cout << 'X';
+					missingSectors++;
+				}
+				else
+				{
+					switch (sector->status)
+					{
+						case Sector::OK:
+                            std::cout << '.';
+                            break;
+
+                        case Sector::BAD_CHECKSUM:
+                            std::cout << 'B';
+                            badSectors++;
+                            break;
+
+                        case Sector::CONFLICT:
+                            std::cout << 'C';
+                            badSectors++;
+                            break;
+
+                        default:
+                            std::cout << '?';
+                            break;
+                    }
+				}
+				totalSectors++;
+			}
+			std::cout << std::endl;
+		}
+	}
+	int goodSectors = totalSectors - missingSectors - badSectors;
+	if (totalSectors == 0)
+		std::cout << "No sectors in output; skipping analysis" << std::endl;
+	else
+	{
+		std::cout << "Good sectors: " << goodSectors << "/" << totalSectors
+				  << " (" << (100*goodSectors/totalSectors) << "%)"
+				  << std::endl;
+		std::cout << "Missing sectors: " << missingSectors << "/" << totalSectors
+				  << " (" << (100*missingSectors/totalSectors) << "%)"
+				  << std::endl;
+		std::cout << "Bad sectors: " << badSectors << "/" << totalSectors
+				  << " (" << (100*badSectors/totalSectors) << "%)"
+				  << std::endl;
+    }
+}

lib/imagewriter/imagewriter.h

@@ -0,0 +1,45 @@
+#ifndef IMAGEWRITER_H
+#define IMAGEWRITER_H
+
+class SectorSet;
+class ImageSpec;
+
+class ImageWriter
+{
+public:
+	ImageWriter(const SectorSet& sectors, const ImageSpec& spec);
+	virtual ~ImageWriter() {};
+
+public:
+    static std::unique_ptr<ImageWriter> create(const SectorSet& sectors, const ImageSpec& spec);
+	static void verifyImageSpec(const ImageSpec& filename);
+
+private:
+	typedef 
+		std::function<
+			std::unique_ptr<ImageWriter>(const SectorSet& sectors, const ImageSpec& spec)
+		>
+		Constructor;
+
+	static std::map<std::string, Constructor> formats;
+
+    static std::unique_ptr<ImageWriter> createImgImageWriter(
+		const SectorSet& sectors, const ImageSpec& spec);
+    static std::unique_ptr<ImageWriter> createLDBSImageWriter(
+		const SectorSet& sectors, const ImageSpec& spec);
+    static std::unique_ptr<ImageWriter> createD64ImageWriter(
+		const SectorSet& sectors, const ImageSpec& spec);
+
+	static Constructor findConstructor(const ImageSpec& spec);
+
+public:
+	virtual void adjustGeometry();
+	void printMap();
+	virtual void writeImage() = 0;
+
+protected:
+	const SectorSet& sectors;
+	ImageSpec spec;
+};
+
+#endif

lib/imagewriter/imgimagewriter.cc

@@ -0,0 +1,62 @@
+#include "globals.h"
+#include "image.h"
+#include "flags.h"
+#include "dataspec.h"
+#include "sector.h"
+#include "sectorset.h"
+#include "imagewriter/imagewriter.h"
+#include "fmt/format.h"
+#include <algorithm>
+#include <iostream>
+#include <fstream>
+
+class ImgImageWriter : public ImageWriter
+{
+public:
+	ImgImageWriter(const SectorSet& sectors, const ImageSpec& spec):
+		ImageWriter(sectors, spec)
+	{}
+
+	void writeImage()
+	{
+		unsigned numCylinders = spec.cylinders;
+		unsigned numHeads = spec.heads;
+		unsigned numSectors = spec.sectors;
+		unsigned numBytes = spec.bytes;
+
+		size_t headSize = numSectors * numBytes;
+		size_t trackSize = headSize * numHeads;
+
+		std::cout << fmt::format("writing {} tracks, {} heads, {} sectors, {} bytes per sector, {} kB total",
+						numCylinders, numHeads,
+						numSectors, numBytes,
+						numCylinders * trackSize / 1024)
+				<< std::endl;
+
+		std::ofstream outputFile(spec.filename, std::ios::out | std::ios::binary);
+		if (!outputFile.is_open())
+			Error() << "cannot open output file";
+
+		for (int track = 0; track < numCylinders; track++)
+		{
+			for (int head = 0; head < numHeads; head++)
+			{
+				for (int sectorId = 0; sectorId < numSectors; sectorId++)
+				{
+					const auto& sector = sectors.get(track, head, sectorId);
+					if (sector)
+					{
+						outputFile.seekp(sector->logicalTrack*trackSize + sector->logicalSide*headSize + sector->logicalSector*numBytes, std::ios::beg);
+						outputFile.write((const char*) sector->data.cbegin(), sector->data.size());
+					}
+				}
+			}
+		}
+	}
+};
+
+std::unique_ptr<ImageWriter> ImageWriter::createImgImageWriter(
+	const SectorSet& sectors, const ImageSpec& spec)
+{
+    return std::unique_ptr<ImageWriter>(new ImgImageWriter(sectors, spec));
+}

lib/imagewriter/ldbsimagewriter.cc

@@ -0,0 +1,107 @@
+#include "globals.h"
+#include "image.h"
+#include "flags.h"
+#include "dataspec.h"
+#include "sector.h"
+#include "sectorset.h"
+#include "imagewriter/imagewriter.h"
+#include "fmt/format.h"
+#include "ldbs.h"
+#include <algorithm>
+#include <iostream>
+#include <fstream>
+
+class LDBSImageWriter : public ImageWriter
+{
+public:
+	LDBSImageWriter(const SectorSet& sectors, const ImageSpec& spec):
+		ImageWriter(sectors, spec)
+	{}
+
+	void writeImage()
+	{
+        LDBS ldbs;
+
+		unsigned numCylinders = spec.cylinders;
+		unsigned numHeads = spec.heads;
+		unsigned numSectors = spec.sectors;
+		unsigned numBytes = spec.bytes;
+		std::cout << fmt::format("writing {} tracks, {} heads, {} sectors, {} bytes per sector",
+						numCylinders, numHeads,
+						numSectors, numBytes)
+				<< std::endl;
+
+        Bytes trackDirectory;
+        ByteWriter trackDirectoryWriter(trackDirectory);
+        int trackDirectorySize = 0;
+        trackDirectoryWriter.write_le16(0);
+
+		for (int track = 0; track < numCylinders; track++)
+		{
+			for (int head = 0; head < numHeads; head++)
+			{
+                Bytes trackHeader;
+                ByteWriter trackHeaderWriter(trackHeader);
+
+                int actualSectors = 0;
+				for (int sectorId = 0; sectorId < numSectors; sectorId++)
+				{
+					const auto& sector = sectors.get(track, head, sectorId);
+					if (sector)
+                        actualSectors++;
+                }
+
+                trackHeaderWriter.write_le16(0x000C); /* offset of sector headers */
+                trackHeaderWriter.write_le16(0x0012); /* length of each sector descriptor */
+                trackHeaderWriter.write_le16(actualSectors);
+                trackHeaderWriter.write_8(0); /* data rate unknown */
+                trackHeaderWriter.write_8(0); /* recording mode unknown */
+                trackHeaderWriter.write_8(0); /* format gap length */
+                trackHeaderWriter.write_8(0); /* filler byte */
+                trackHeaderWriter.write_le16(0); /* approximate track length */
+
+				for (int sectorId = 0; sectorId < numSectors; sectorId++)
+				{
+					const auto& sector = sectors.get(track, head, sectorId);
+					if (sector)
+					{
+                        uint32_t sectorLabel = (('S') << 24) | ((track & 0xff) << 16) | (head << 8) | sectorId;
+                        uint32_t sectorAddress = ldbs.put(sector->data, sectorLabel);
+
+                        trackHeaderWriter.write_8(track);
+                        trackHeaderWriter.write_8(head);
+                        trackHeaderWriter.write_8(sectorId);
+                        trackHeaderWriter.write_8(0); /* power-of-two size */
+                        trackHeaderWriter.write_8((sector->status == Sector::OK) ? 0x00 : 0x20); /* 8272 status 1 */
+                        trackHeaderWriter.write_8(0); /* 8272 status 2 */
+                        trackHeaderWriter.write_8(1); /* number of copies */
+                        trackHeaderWriter.write_8(0); /* filler byte */
+                        trackHeaderWriter.write_le32(sectorAddress);
+                        trackHeaderWriter.write_le16(0); /* trailing bytes */
+                        trackHeaderWriter.write_le16(0); /* approximate offset */
+                        trackHeaderWriter.write_le16(sector->data.size());
+					}
+				}
+
+                uint32_t trackLabel = (('T') << 24) | ((track & 0xff) << 16) | ((track >> 8) << 8) | head;
+                uint32_t trackHeaderAddress = ldbs.put(trackHeader, trackLabel);
+                trackDirectoryWriter.write_be32(trackLabel);
+                trackDirectoryWriter.write_le32(trackHeaderAddress);
+                trackDirectorySize++;
+			}
+		}
+
+        trackDirectoryWriter.seek(0);
+        trackDirectoryWriter.write_le16(trackDirectorySize);
+
+        uint32_t trackDirectoryAddress = ldbs.put(trackDirectory, LDBS_TRACK_BLOCK);
+        Bytes data = ldbs.write(trackDirectoryAddress);
+        data.writeToFile(spec.filename);
+    }
+};
+
+std::unique_ptr<ImageWriter> ImageWriter::createLDBSImageWriter(
+	const SectorSet& sectors, const ImageSpec& spec)
+{
+    return std::unique_ptr<ImageWriter>(new LDBSImageWriter(sectors, spec));
+}

lib/ldbs.cc

@@ -0,0 +1,81 @@
+#include "globals.h"
+#include <string.h>
+#include "bytes.h"
+#include "ldbs.h"
+#include "fmt/format.h"
+
+LDBS::LDBS()
+{}
+
+uint32_t LDBS::put(const Bytes& data, uint32_t type)
+{
+    uint32_t address = top;
+    Block& block = blocks[address];
+    block.type = type;
+    block.data = data;
+
+    top += data.size() + 20;
+    return address;
+}
+
+uint32_t LDBS::read(const Bytes& data)
+{
+    ByteReader br(data);
+
+    br.seek(0);
+    if ((br.read_be32() != LDBS_FILE_MAGIC)
+        || (br.read_be32() != LDBS_FILE_TYPE))
+        Error() << "not a valid LDBS file";
+
+    uint32_t address = br.read_le32();
+    br.skip(4);
+    uint32_t trackDirectory = br.read_le32();
+
+    while (address)
+    {
+        br.seek(address);
+        if (br.read_be32() != LDBS_BLOCK_MAGIC)
+            Error() << fmt::format("invalid block at address 0x{:x}", address);
+
+        Block& block = blocks[address];
+        block.type = br.read_be32();
+
+        uint32_t size = br.read_le32();
+        br.skip(4);
+        address = br.read_le32();
+
+        block.data.writer().append(br.read(size));
+    }
+        
+    top = data.size();
+    return trackDirectory;
+}
+
+const Bytes LDBS::write(uint32_t trackDirectory)
+{
+    Bytes data(top);
+    ByteWriter bw(data);
+
+    uint32_t previous = 0;
+    for (const auto& e : blocks)
+    {
+        bw.seek(e.first);
+        bw.write_be32(LDBS_BLOCK_MAGIC);
+        bw.write_be32(e.second.type);
+        bw.write_le32(e.second.data.size());
+        bw.write_le32(e.second.data.size());
+        bw.write_le32(previous);
+        bw.append(e.second.data);
+
+        previous = e.first;
+    }
+
+    bw.seek(0);
+    bw.write_be32(LDBS_FILE_MAGIC);
+    bw.write_be32(LDBS_FILE_TYPE);
+    bw.write_le32(previous);
+    bw.write_le32(0);
+    bw.write_le32(trackDirectory);
+    
+    return data;
+}