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9154327d2eb34f548c8d39949213fda892418215
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Author SHA1 Message Date
Bruno Levy
9154327d2e Precision: for Ubuntu 2022-11-24 18:14:52 +01:00
Bruno Levy
1ccf098e7a New script to install YOSYS/NEXTPNR for ICE40-based FPGAs 2022-11-24 18:14:09 +01:00
Bruno Levy
0a97ede525 * Added precompiled RAYSTONES, DHRYSONES and COREMARK 
* Experimental pipelineZ.v with two shifters (left and right), and
  pipelined register Id comparison.
 2022-10-12 15:57:05 +02:00
Bruno Levy
cecdaf7a8f * Added new frequencies in PLL (now we got something that runs 
at 180 MHz on the ULX3S)
* Added (* no_rw_check *) where relevant in femtosoc and quark
 2022-10-02 19:22:45 +02:00
Bruno Levy
dd7b10b416 typos. 2022-09-26 12:41:53 +02:00
Bruno Levy
7ae0d3205f Added step on RV32M 2022-09-25 22:53:05 +02:00
Bruno Levy
55a61df815 typo ! 2022-09-25 10:01:00 +02:00
Bruno Levy
c802104a75 Small fixes in step 9 2022-09-25 09:55:18 +02:00
Bruno Levy
5e49257292 BRAM, not DRAM ! 2022-09-25 09:45:14 +02:00
Bruno Levy
2ef4bf4e44 Finished writing tutorial for step 9 (RAS) 2022-09-25 09:44:43 +02:00
Bruno Levy
a750d57362 Restored % 21 instead of & 15 (now we have div/rem in pipelineY.v) 2022-09-19 23:02:00 +02:00
Bruno Levy
0bbee839cd better "progress bar"... 2022-09-19 14:59:27 +02:00
Bruno Levy
587f5a7573 * added missing .section DATA in assembly programs 
* raystones: added "progress bar"
* pipelineY.v: added MUL/DIV stats
 2022-09-19 14:55:13 +02:00
Bruno Levy
9e08dcec74 cCleanup, comments. 2022-09-18 20:12:46 +02:00
Bruno Levy
e6ad7e38e9 Ooops, `ifdef RV32M instead of CONFIG_RV32M broke everything !!! 2022-09-18 19:48:34 +02:00
Bruno Levy
f252a96853 Comments 2022-09-18 19:45:04 +02:00
Bruno Levy
e98c91ae06 Made RV32M optional 2022-09-18 19:44:04 +02:00
Bruno Levy
dafd0f9268 Replaced several imbrications of muxes with big "or" expression in 
MUL/DIV ALU.
 2022-09-18 19:09:23 +02:00
Bruno Levy
631db7b065 Added comments. 2022-09-18 18:49:52 +02:00
Bruno Levy
42c2ebbbcc cleaner division. 2022-09-18 18:42:53 +02:00
Bruno Levy
837c5eefab cleaner divide, without divResult reg (now uses mux on 
EE_quotient and EE_dividend)
 2022-09-18 17:56:39 +02:00
Bruno Levy
5d21128738 - Removed registered branch prediction (does not gain anything) 
- Registered DE_isDiv and EE_DivBusy
 2022-09-18 15:45:29 +02:00
Bruno Levy
e82bc09c72 300 iterations (else not enough to measure timings) 2022-09-18 08:09:38 +02:00
Bruno Levy
503b0b790a Fixed load-after-store bug by inserting a bubble : 
added || (D_isLoad && DE_isStore) to dataHazard
    condition.
 2022-09-18 07:49:50 +02:00
Bruno Levy
9bd5b94c37 Found bug in pipelineX and pipelineY: when storing at an address and 
loading at the same address in the next instruction, wrong value is
obtained because load memory access is done in Execute.
 2022-09-18 07:18:52 +02:00
Bruno Levy
3f4ee1fbfd - Added reg fwd display in debug. 
- WIP: DIV/REM
 2022-09-17 09:30:08 +02:00
Bruno Levy
e63efbcf59 pipelineY: added MUL instructions 
riscv_disassembly: added RV32M instructions
 2022-09-16 21:08:54 +02:00
Bruno Levy
68261c87eb Added "debugger" 2022-09-16 15:25:56 +02:00
Bruno Levy
261d75ff29 Comment. 2022-09-16 10:38:30 +02:00
Bruno Levy
0d49dee78b Fixed computation of load hazard statistics 
(instructions were wrongly put in if(!D_stall) conditional)
 2022-09-16 10:33:39 +02:00
Bruno Levy
2e9f7027aa Added statistic in bench mode. 2022-09-16 10:28:21 +02:00
Bruno Levy
69244a8356 * riscv_disassembly.v: added utility functions in riscv_disasm (RV32I instruction recognizers and field extraction) 
* pipelineX_generic.v: improved debugger
 2022-09-16 09:56:11 +02:00
Bruno Levy
91e5a4ef5c Added generic version of optimized pipelined CPU. 2022-09-16 04:02:46 +02:00
Bruno Levy
1d4df16794 More optimizations in D stage, and registered D_predictBranch. 2022-09-14 14:34:16 +02:00
Bruno Levy
6b042d001e Cleanup 2022-09-09 14:38:49 +02:00
Bruno Levy
5ee0184d07 PipelineX: Added versions with register fwding alone, static branch prediction, 
return address stack.
 2022-09-08 23:45:33 +02:00
Bruno Levy
e9401388c5 Added support for ARTY 2022-09-07 21:46:39 +02:00
Bruno Levy
b116c81b49 Added coremark benchmark (adapted) 2022-09-07 21:45:46 +02:00
Bruno Levy
192d679b42 * fixed problem in dhrystone (uint64_t everywhere, and run it 50000 
time instead of 100 to mitigate "startup code" discrepancy between
  measured CPI in test and in VERILOG code)
* added Load/Store stats and Load hazard stats in pipeline9.v
 2022-09-06 08:41:05 +02:00
Bruno Levy
362d869768 - Fixed Return Address Stack (test both x1 and x5 for JALR as "ret") 
- pipelineX.v: comments at beginning of file.
 2022-09-05 14:59:11 +02:00
Bruno Levy
8feb9f3c37 - aesthetic fix. 
- Return Address Stack: pushes more often than it pops, still
investigating...
 2022-09-05 08:29:32 +02:00
Bruno Levy
ac47b239b8 Finished step 8 on branch prediction. 2022-09-04 12:19:05 +02:00
Bruno Levy
dd304e4e52 gshare branch prediction seems to work. 2022-09-04 10:58:58 +02:00
Bruno Levy
35368da0ef Branch prediction 
- added DHRYSTONE test
   - cleaning sources, adding hit/miss reports in simulation
   - pipeline9.v: with return address stack
 2022-09-03 10:50:26 +02:00
Bruno Levy
629b48b24e pshare/gshare 2022-08-31 15:37:20 +02:00
Bruno Levy
7ec9dd1097 Cleaner and commented dynamic branch prediction 2022-08-31 14:01:42 +02:00
Bruno Levy
a2b5f94023 cleaner stats. 2022-08-31 13:49:08 +02:00
Bruno Levy
9fea7a3e2b dynamic branch prediction. 2022-08-31 13:14:51 +02:00
Bruno Levy
16b1b85489 Fixed verbose mode for version with branch prediction 2022-08-29 22:18:08 +02:00
Bruno Levy
3576c7ad1f pipeline7 now gives stats on branch prediction in simulation. 2022-08-29 19:21:36 +02:00