mux16

Makefile

@@ -1,6 +1,15 @@
 clean:
 	-rm *.vcd *.vvp
 
+mux16_tb: mux16_tb.vcd
+	gtkwave mux16_tb.vcd &
+
+mux16_tb.vcd: mux16_tb.vvp
+	vvp mux16_tb.vvp
+
+mux16_tb.vvp: mux16.v mux16_tb.v
+	iverilog -o mux16_tb.vvp mux16_tb.v
+
 or16_tb: or16_tb.vcd
 	gtkwave or16_tb.vcd &
 

mux16.v

@@ -0,0 +1,15 @@
+`ifndef _mux16_v
+`define _mux16_v
+
+`include "mux.v"
+
+module Mux16 (input [15:0] a, input [15:0] b, input sel, output [15:0] out);
+
+    genvar i;
+    generate
+        for (i=0; i<16; i=i+1)
+            Mux u1 (.a(a[i]), .b(b[i]), .sel(sel), .out(out[i]));
+    endgenerate
+endmodule
+
+`endif

mux16_tb.v

@@ -0,0 +1,35 @@
+`include "mux16.v"
+
+module Mux16_test;
+    reg [15:0] a, b;
+    reg sel;
+    wire [15:0] out;
+
+    integer i, j;
+
+    initial begin
+        $dumpfile("mux16_tb.vcd");
+        $dumpvars;
+        for (i=0; i<16; i=i+1)
+        begin
+            a[i]=0;
+            b[i]=0;
+        end
+        for (i=15; i>=0; i=i-1)
+        begin
+            for (j=0; j<8; j=j+1)
+            begin
+                sel=(j&4)>>2;
+                b[i]=(j&2)>>1;
+                a[i]=j&1;
+                #1;
+            end
+            sel=0;
+            a[i]=0;
+            b[i]=0;
+        end
+        $finish();
+    end
+
+    Mux16 u1 (.a(a), .b(b), .sel(sel), .out(out));
+endmodule