salfter/fluxengine
1
0
Fork 0
mirror of https://github.com/davidgiven/fluxengine.git synced 2025-10-31 11:17:01 -07:00
Code Issues Packages Projects Releases Wiki Activity
1,336 Commits 56 Branches 83 Tags
bcf6f48d46c0a08f02fe418fa366a2d3207c7cfc
Commit Graph

138 Commits

Author SHA1 Message Date
David Given
5f4f2f10d7 Update FluxEngine components and rebuild firmware. 2021-05-25 19:11:32 +01:00
Howard M. Harte
42f858267c Hard Sectors: Fix index_irq assertion. 
The index_irq could trigger one sector too late, in the case where
index_irq was reset just before the sector pulse was received.

Check the duration of the time between pulses before propagating the
hardsec_index_irq_primed to index_irq.

While this change is required for reading and writing North Star
floppies (due to lack of positioning information in the sector header)
it is also helpful for reading Micropolis disks, as currently,
occasionally the first sector will be missed, and will be found on the
next rotation of the disk.  This change is required for reliably writing
Micropolis disks though, when that functionality becomes available.
 2021-05-16 15:41:55 -07:00
David Given
27c2c9045e Update sequencer to not lose one tick from every non-zero interval. 2021-01-18 00:27:00 +01:00
David Given
c2c51bbe33 Fix after merge. 2021-01-09 00:02:14 +01:00
David Given
a11d0e75c8 Merge pull request #200 from ejona86/hard-sectors 
Add firmware support for hard sectors
 2021-01-08 23:20:40 +01:00
David Given
e53b7ecd8b Rebuild firmware. 2021-01-05 01:51:29 +01:00
David Given
7d88673ed5 Merge from trunk. 2021-01-05 01:36:54 +01:00
David Given
884edfd497 Tweak the Mac encoder parameters to work. 2021-01-04 23:06:15 +01:00
David Given
83dd9e462e Fix sequencer bug where intervals of 0 would go horribly wrong. 2021-01-04 22:06:19 +01:00
David Given
7f5d96382b Update PSoC components. 2021-01-04 20:16:15 +01:00
Eric Anderson
f1506d0dbd Add firmware support for hard sectors 2020-12-24 17:39:52 -08:00
David Given
b374340303 Try multiplexing SIDE1 onto DIR. 2020-09-10 22:07:47 +02:00
David Given
c78ed2c6ad Add the TK43 pin, which goes low when seeking to track 43 or above. 2020-09-10 21:48:30 +02:00
David Given
d60900262b Remove the pulse converters from the sampler (the new sampler doesn't require 
them). Update firmware.
 2020-06-25 21:07:58 +02:00
David Given
54ea34400b Merge in jboone's updated sampler branch. 2020-06-25 21:01:35 +02:00
Jared Boone
db2ab8841a Update Sampler.v, moving clock domain crossing to FIFO interface. 
Hopefully, I unscrewed the tab/space and line ending mismatches to minimize the diff.
 2020-05-30 21:31:17 -07:00
Jared Boone
adb9809692 Simplify Sampler. 2020-05-20 11:34:29 -07:00
David Given
2b53ac057c Fix some bugs which allow erasing tracks with F_FRAME_WRITE_CMD to work again. 
(F_FRAME_ERASE_CMD always worked.)
 2020-05-13 23:45:58 +02:00
David Given
a9e30c1e49 Fix an off-by-one error in the sequencer that should have it generating correct 
sequences.
 2020-04-03 22:58:51 +02:00
David Given
972c8c6b61 Fix off-by-one sampler error, so now the clock rates are right again. 2020-04-03 22:27:33 +02:00
David Given
64694580cd Remember to bump the protocol number after the bytecode change. 2020-04-03 21:46:51 +02:00
David Given
0644d6d965 Remove some stray tracing (which was causing problems). Fix a potential problem 
where sampleclock posedges could be lost in the sequencer.
 2020-03-29 23:11:53 +02:00
David Given
a075694d8e Rewrite the sequencer to work with the new six bit bytecode. Fiddle with the 
USB stuff a lot in an attempt to resolve the weird packet loss issue.
 2020-03-29 15:10:35 +02:00
David Given
00087cbb6b Fix a catastrophic DMA setup bug which was causing (probably) every other byte 
of data to be mixed up with every other byte... but as every other byte was a
0x80 we never noticed up until now.
 2020-03-20 00:06:58 +01:00
David Given
1b48ea20c4 Remove the cruncher. 2020-03-20 00:06:07 +01:00
David Given
3d0f019fc4 Replace the sampler with one using the new simplified bytecode. 2020-03-19 23:39:23 +01:00
David Given
1025bd857b Don't crashloop if the USB's not connected, as it causes the drives to be 
constantly reprobed (which runs the motor).
 2020-02-27 22:32:27 +01:00
David Given
c47a563790 Don't seek to track -1 on homing (it appears to upset 8" drives). Detect which 
drives are present, so that if only a single drive is attached then it's always
track 0, regardless of which connector it's on.
 2020-02-24 21:47:40 +01:00
David Given
647862cdbd Update the firmware for the new cruncher. 2020-02-18 22:13:41 +01:00
David Given
2df9920209 Rename test bulktransport to test bandwidth; avoid watchdog failures while the 
bandwidth test is running.
 2020-02-18 19:12:52 +01:00
David Given
1a6c6b5420 The bandwidth tester now tests bandwidth in both directions. It looks like my 
default USB port only gets about 500kB/s write bandwidth. However, when plugged
into a port with 850kB/s, I still get underrun errors...
 2020-02-17 23:58:40 +01:00
David Given
edc56d44d6 Non-functioning archive checkin: You can only have 120-odd DMA buffers, so my 
last 'fix' was in fact non-functional.
 2020-02-17 23:28:40 +01:00
David Given
ef4eff0195 So writing now works, but only if USB DMA is enabled. But that breaks reading. 
I've worked round this in a simple but brute force manner and it now looks as
if reading *and* writing work, more or less. There does still seem to be the
odd bad sector when writing 1440kB disks.
 2020-02-17 21:41:01 +01:00
David Given
df8d45bf66 Rework the output fifo to be a bit more correct about the sync signals, which 
in turn allows the sequencer to lose less time --- this gets the effective
clock rate down to about 1.01us. However we still seem to lose the last sector
on 18-sector disks and there are some disk reads so something is still wrong.
 2020-02-17 00:13:13 +01:00
David Given
387a86969a Some verilog optimisations which shave off a few p-terms. 2020-02-15 12:15:51 +01:00
David Given
acb5059d17 Rewrite the sampler *again* to, hopefully, be more stable and not lose ticks. 
Luckily, we have just enough space in the FPGA to use an actual logic counter,
which simplifies things hugely.
 2020-02-15 12:09:19 +01:00
David Given
29bdfc043a Allow fractional revolutions and non-synced reading. Find more things which 
need fixing in the firmware sampler.
 2020-01-27 22:52:25 +01:00
David Given
933ffe7ab4 Find and attempt to fix a memory corruption error when sampling --- if the next 
fragment arrives from the sampler before usbbuffer has finished being
transmitted via USB, it'll get overwritten. I've disabled DMA USB to make the
code easier to understand and made sure that we flush things more rigorously.
This may help the weird pipe errors, too.
 2020-01-27 21:40:27 +01:00
David Given
b0c675c589 Improved error messages when using fe-rpm and it doesn't work. 2020-01-12 01:34:12 +01:00
David Given
d77841c3b7 Add the ability to fake the index pulse source, allowing old drives to be used 
with FluxEngine.
 2020-01-12 01:23:47 +01:00
David Given
bcc9e9d9a5 Bump the protocol number (I forgot last time I changed the protocol). 2020-01-10 21:04:33 +01:00
David Given
6389e8a756 Update pin number (which was wrong). 2019-12-12 20:35:20 +01:00
David Given
c187b79d80 Add a 300RPM clock on 3[0] and a 360RPM clock on 3[1], for use with faking 
index pulses to the drive.
 2019-12-12 20:34:44 +01:00
David Given
edbe624c5a Hopefully, finally, fix the hang-on-read issue. 2019-12-12 20:09:49 +01:00
David Given
44e2334815 Typo fix. Make sure that both drives get deselected when the motor stops (to 
make the LEDs go out).
 2019-12-12 00:17:59 +01:00
David Given
b448ab7917 Finally squeeze everything in to the Verilog sampler. It does seem to work 
better... the the USB hangup problem persists. Mac disks are still
nigh-unreadable.
 2019-12-12 00:12:20 +01:00
David Given
072a097003 Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've 
run into size limits for the device, and I need to slim down.
 2019-12-11 22:51:27 +01:00
David Given
a66e704bab Start ripping out the awful UDB-based sampler code, replacing it with a Verilog 
one and a standalone FIFO. This gets the FIFO working.
 2019-12-11 21:13:57 +01:00
David Given
32bb956710 Detect voltage levels *correctly*. 2019-12-11 00:05:34 +01:00
David Given
f436d6b582 Add a feature where we can measure the FDD bus signal voltages using the PSoC's 
ADCs. Increase the track step pulse width to 6us, because.
 2019-12-10 22:36:18 +01:00