|
|
70d5fd8715
|
blinky: update makefile
(can't get Verilator to work yet due to PLL usage)
|
2025-08-22 15:08:39 -07:00 |
|
|
|
5cb0b79110
|
add PLL to blinky
|
2025-08-21 15:32:14 -07:00 |
|
|
|
5fd2a484e5
|
.
|
2025-08-19 08:17:41 -07:00 |
|
|
|
53563a2c93
|
can't get the 6502 core to build...it seems to be skipped
|
2025-08-14 15:29:46 -07:00 |
|
|
|
130b3e8afc
|
udpated README
|
2025-08-14 13:07:35 -07:00 |
|
|
|
93cc9ea149
|
add documentation for MSYS2
|
2025-08-14 12:54:57 -07:00 |
|
|
|
33f682cb53
|
.
|
2025-08-14 07:23:04 -07:00 |
|
|
|
1019422be6
|
gate: simulate with Verilator
|
2025-08-13 17:31:56 -07:00 |
|
|
|
f6f75e3941
|
add README
|
2025-08-13 15:23:58 -07:00 |
|
|
|
794d9586b5
|
modify TinyFPGA BX template for nextpnr & verilator; do thruwire tutorial from https://zipcpu.com/tutorial/lsn-01-wires.pdf
|
2025-08-13 15:05:18 -07:00 |
|
|
|
831e6ece8b
|
.
|
2025-08-12 15:36:21 -07:00 |
|
|
|
7c1c3a1be7
|
gate currently contains a divide-by-3 counter
|
2025-08-12 14:09:27 -07:00 |
|
|
|
9ca934eebb
|
rearrange blinkies
|
2025-08-11 08:33:17 -07:00 |
|
|
|
90e1d6d755
|
blinky is mostly where we want it to be
|
2025-08-09 10:40:18 -07:00 |
|
|
|
ac84bd1227
|
.
|
2025-08-08 19:10:17 -07:00 |
|
|
|
44d224c8a8
|
upduino blinky (testbench not working)
|
2025-08-08 14:39:10 -07:00 |
|
|
|
8850c4a962
|
include UPduino repo
|
2025-08-08 08:35:16 -07:00 |
|
|
|
0f26ca1ab2
|
initial commit: setbit configured for TinyFPGA-BX
|
2025-08-08 08:09:03 -07:00 |
|
