Bastian Löher
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b2b67d191c
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Add pseudo instructions in assembler. Add step 14 with pseudo instructions.
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2023-02-05 01:57:18 +01:00 |
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Bastian Löher
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ba88db9a79
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Add step 13 (makeshift wait function). Bug in Amaranth got fixed, so can use Repl() again.
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2023-01-18 02:36:49 +01:00 |
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Bastian Löher
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47fe7bee36
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Add step 12 in top.
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2023-01-16 10:30:13 +01:00 |
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Bastian Löher
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33760eb512
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Merge pull request #1 from bl0x/add-license-1
Create LICENSE
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2023-01-13 01:57:57 +01:00 |
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Bastian Löher
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5ec7dc04aa
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Create LICENSE
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2023-01-13 01:57:36 +01:00 |
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Bastian Löher
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c0c7cda799
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Add README.
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2023-01-13 01:51:00 +01:00 |
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Bastian Löher
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10595b068d
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Avoid bug when using Repl.
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2023-01-13 01:28:02 +01:00 |
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Bastian Löher
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89559d21aa
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Add boards directory with a generic top and platform specific modules.
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2023-01-12 22:38:33 +01:00 |
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Bastian Löher
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22f228e3e8
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Simplify cpu a bit.
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2023-01-12 21:50:10 +01:00 |
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Bastian Löher
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abdfbf2106
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Split soc into several modules.
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2022-12-07 01:41:08 +01:00 |
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Bastian Löher
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b133b7ccd3
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Add step10. LUI AUIPC.
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2022-12-07 00:49:51 +01:00 |
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Bastian Löher
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1452f27819
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Fix up encodeI.
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2022-12-07 00:49:13 +01:00 |
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Bastian Löher
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791f99dbae
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Improve riscv_assembler: fix encodeI, support for 0b and 0x literals.
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2022-12-07 00:41:35 +01:00 |
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Bastian Löher
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47cb30695d
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Add step9 / branches.
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2022-12-05 12:54:18 +01:00 |
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Bastian Löher
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c4af443ef0
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Add 08_jumps.
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2022-12-05 12:25:33 +01:00 |
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Bastian Löher
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f920a83be7
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Change pc to point to address instead of intstruction index.
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2022-12-05 12:13:42 +01:00 |
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Bastian Löher
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8452062785
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Add rest of the instructions.
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2022-12-05 12:07:45 +01:00 |
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Bastian Löher
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a3c011ee31
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Start step7 with riscv assembler.
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2022-12-05 10:58:54 +01:00 |
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Bastian Löher
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25e30c4675
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fsm must run in 'slow' domain. alu must be combinatorial.
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2022-12-05 10:44:03 +01:00 |
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Bastian Löher
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4e74cd693d
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Add slow_sim parameter to clockworks. Add step6 / alu.
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2022-12-05 08:38:34 +01:00 |
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Bastian Löher
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9953f650e1
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Whitespace.
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2022-12-05 04:05:29 +01:00 |
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Bastian Löher
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1142905f01
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Add step5.
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2022-12-05 04:05:18 +01:00 |
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Bastian Löher
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142281b3a9
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Reorder.
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2022-12-05 03:34:02 +01:00 |
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Bastian Löher
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70fea04527
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Simplify signals. Export operators as signals for simulation.
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2022-12-05 03:33:27 +01:00 |
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Bastian Löher
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21b1caad54
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Working step4.
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2022-12-05 02:37:30 +01:00 |
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Bastian Löher
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77dd6812b4
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Fix SW instruction (swap rs1 rs2) in assembler.
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2022-12-05 01:17:44 +01:00 |
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Bastian Löher
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5a8b018928
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Move clockworks to lib. Add env.sh for PYTHONPATH. Fix step03.
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2022-12-05 00:38:11 +01:00 |
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Bastian Löher
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a30d0245f7
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Fixup.
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2022-12-03 02:54:02 +01:00 |
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Bastian Löher
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7e23408991
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Support for labels.
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2022-12-03 02:50:37 +01:00 |
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Bastian Löher
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4222ee9e9e
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Support for abi names. Some system ops.
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2022-12-03 02:37:41 +01:00 |
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Bastian Löher
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f7b533dc11
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Start riscv assembler.
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2022-12-03 02:12:39 +01:00 |
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Bastian Löher
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446aed23d5
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Add step3.
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2022-12-03 02:12:22 +01:00 |
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Bastian Löher
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e95a456d1a
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Add step2.
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2022-12-01 16:48:41 +01:00 |
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Bastian Löher
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a105362b0a
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Factor out SOC and add bench test.
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2022-12-01 16:07:26 +01:00 |
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Bastian Löher
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03c9fadba6
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Initial commit.
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2022-12-01 15:29:39 +01:00 |
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