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727189c037
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bit: timing's a bit wonky
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2024-06-17 10:11:07 -07:00 |
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8c9d751841
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dff: switch to Verilog primitives to get edge triggering
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2024-06-14 16:13:09 -07:00 |
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617be7a69f
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D flip-flop (currently level-triggered; should make it edge-triggered)
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2024-06-14 15:01:28 -07:00 |
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981d7a4d6f
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Update alu_tb.v
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2024-06-14 13:55:39 -07:00 |
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c7984ae883
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ALU
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2024-06-14 08:04:43 -07:00 |
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ec1a0731cd
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16-bit increment
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2024-06-13 21:19:30 -07:00 |
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a7f7723702
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16-bit adder
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2024-06-13 21:13:15 -07:00 |
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bebe8fa2d0
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half and full adders
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2024-06-13 19:58:39 -07:00 |
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23220d1004
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1-to-8 demux
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2024-06-13 19:00:21 -07:00 |
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66539bedd9
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1-to-4 demux
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2024-06-13 18:55:53 -07:00 |
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353fe40507
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16-bit 8-to-1 mux
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2024-06-13 18:28:20 -07:00 |
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2bbde06bec
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16-bit 4-to-1 mux
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2024-06-13 18:21:15 -07:00 |
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2e3c6ee9b1
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8-to-1 mux
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2024-06-13 17:52:12 -07:00 |
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24afea91ca
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4-to-1 mux
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2024-06-13 15:29:23 -07:00 |
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daf36c466c
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8-input OR
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2024-06-13 14:43:34 -07:00 |
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f4f91ab870
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mux16
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2024-06-13 14:23:05 -07:00 |
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9a1e98ba2e
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and16 and or16
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2024-06-13 14:12:48 -07:00 |
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ee78a17a90
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Demux
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2024-06-13 13:50:03 -07:00 |
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281195694e
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fix module declarations
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2024-06-13 13:29:36 -07:00 |
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a88adbf6e3
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16-bit NOT
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2024-06-13 13:24:54 -07:00 |
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841881d543
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Mux added, and some cleanup
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2024-06-13 13:03:38 -07:00 |
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990bad228c
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XOR: reduced gate count
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2024-06-13 07:51:18 -07:00 |
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5c35313978
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NOR and XOR
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2024-06-12 22:46:10 -07:00 |
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65a0599e3d
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OR gate
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2024-06-12 22:24:45 -07:00 |
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beee8e4587
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AND gate (and some ifdefs)
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2024-06-12 22:19:23 -07:00 |
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fa01e24f2e
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NOT gate
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2024-06-12 22:10:32 -07:00 |
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9d65605f62
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initial commit: implement a NAND gate, and test it
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2024-06-12 22:01:00 -07:00 |
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